ADC08D1520
Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/DConverter
General Description
The ADC08D1520 is a dual, low power, high performanceCMOS analog-to-digital converter that builds upon theADC08D1500 platform. The ADC08D1520 digitizes signals to8 bits of resolution at sample rates up to 1.7 GSPS. It hasexpanded features compared to the ADC08D1500, which in-clude a test pattern output for system debug, a clock phaseadjust, and selectable output demultiplexer modes. Consum-ing a typical 1.6 Watts in Non-Demultiplex Mode at 1.0 GSPSfrom a single 1.9 Volt supply, this device is guaranteed to haveno missing codes over the full operating temperature range.The unique folding and interpolating architecture, the fully dif-ferential comparator design, the innovative design of the in-ternal sample-and-hold amplifier and the self-calibrationscheme enable a very flat response of all dynamic parametersbeyond Nyquist, producing a high 7.4 Effective Number of Bits(ENOB) with a 748 MHz input signal and a 1.5 GHz samplerate while providing a 10-18 Code Error Rate (C.E.R.) Outputformatting is offset binary and the Low Voltage DifferentialSignaling (LVDS) digital outputs are compatible with IEEE1596.3-1996, with the exception of an adjustable commonmode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer whichfeeds two LVDS buses. If the 1:2 Demultiplexed Mode is se-lected, the output data rate is reduced to half the input samplerate on each bus. When Non-Demultiplexed Mode is select-ed, the output data rate on channels DI and DQ is at the samerate as the input sample clock. The two converters can beinterleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in thePower Down Mode and is available in a leaded or lead-free,128-pin, thermally enhanced, exposed pad, LQFP and oper-ates over the Industrial (-40°C ≤ TA ≤ +85°C) temperaturerange.
Features
■■■■■■■■■
Single +1.9V ±0.1V Operation
Interleave Mode for 2x Sample RateMultiple ADC Synchronization Capability
Adjustment of Input Full-Scale Range, Clock Phase, andOffset
Choice of SDR or DDR Output Clocking1:1 or 1:2 Selectable Output DemuxSecond DCLK Output
Duty Cycle Corrected Sample ClockTest pattern
Key Specifications
■■■■■■
Resolution8 BitsMax Conversion Rate1.5 GSPS (max)Code Error Rate10-18 (typ)ENOB @ 748 MHz Input7.4 Bits (typ)DNL±0.15 LSB (typ)Power Consumption (Non-DES Mode)
1.6 W (typ)—Operating in Non-demux Mode
2.0 W (typ)—Operating in 1:2 Demux Mode
3.5 mW (typ)—Power Down Mode
Applications
■
■■■■
Direct RF Down ConversionDigital OscilloscopesSatellite Set-top boxesCommunications SystemsTest Instrumentation
Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
ADC08D1520CIYBADC08D1520CIYB/NOPB
ADC08D1520DEV
NS Package
Leaded 128-Pin Exposed Pad LQFPLead-free 128-Pin Exposed Pad LQFP
Development Board
© 2009 National Semiconductor Corporation201931www.national.com
ADC08D1520Block Diagram
20193153
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ADC08D1520Pin Configuration
20193101
Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.
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ADC08D1520Pin Descriptions and Equivalent Circuits
Pin FunctionsPin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie thispin logic high for normal differential DCLK and data
amplitude. Ground this pin for a reduced differential outputamplitude and reduced power consumption. See 1.1.6 TheLVDS Outputs. When the Extended Control Mode is
enabled, this pin functions as the SCLK input which clocksin the serial data. See 1.2 NON-EXTENDED AND
EXTENDED CONTROL MODE for details on the ExtendedControl Mode. See 1.3 THE SERIAL INTERFACE fordescription of the serial interface.
Power Down Q-channel. A logic high on the PDQ pin putsonly the Q-channel into the Power Down Mode.
DCLK Edge Select, Double Data Rate Enable and SerialData Input. This input sets the output edge of DCLK+ atwhich the output data transitions. See 1.1.5.2 OutEdge andDemultiplex Control Setting. When this pin is floating orconnected to 1/2 the supply voltage, DDR clocking is
enabled. When the Extended Control Mode is enabled, thispin functions as the SDATA input. See 1.2 NON-EXTENDEDAND EXTENDED CONTROL MODE for details on theExtended Control Mode. See 1.3 THE SERIALINTERFACE for description of the serial interface.
DCLK Reset. When single-ended DCLK_RST is selected byfloating or setting pin 52 logic high, a positive pulse on thispin is used to reset and synchronize the DCLK outputs ofmultiple converters. See 1.5 MULTIPLE ADC
SYNCHRONIZATION for detailed description. When
differential DCLK_RST is selected by setting pin 52 logic low,this pin receives the positive polarity of a differential pulsesignal used to reset and synchronize the DCLK outputs ofmultiple converters.
Power Down Pins. A logic high on the PD pin puts the entiredevice into the Power Down Mode.
Calibration Cycle Initiate. A minimum tCAL_L input clock
cycles logic low followed by a minimum of tCAL_H input clockcycles high on this pin initiates the self calibration sequence.See 2.4.2 Calibration for an overview of calibration and2.4.2.2 On-Command Calibration for a description of on-command calibration. The calibration cycle may similarly beinitiated via the CAL bit in the Calibration register (0h).
3OutV / SCLK
29PDQ
4
OutEdge / DDR /
SDATA
15
DCLK_RST /DCLK_RST+
26PD
30CAL
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ADC08D1520Pin FunctionsPin No.
Symbol
Equivalent Circuit
Description
Full Scale Range Select, Alternate Extended Control Enableand DCLK_RST-. This pin has three functions. It can
conditionally control the ADC full-scale voltage, enable theExtended Control Mode, or become the negative polaritysignal of a differential pair in differential DCLK_RST mode.If pin 52 is floating or at logic high and pin 41 is floating, thispin can be used to set the full-scale-range or can be used asan alternate Extended Control Mode enable pin. When usedas the FSR pin, a logic low on this pin sets the full-scaledifferential input range to a reduced VIN input level . A logichigh on this pin sets the full-scale differential input range toa higher VIN input level. See Converter Electrical
Characteristics. To enable the Extended Control Mode,whereby the serial interface and control registers areemployed, allow this pin to float or connect it to a voltageequal to VA/2. See 1.2 NON-EXTENDED AND EXTENDEDCONTROL MODE for information on the Extended ControlMode. Note that pin 41 overrides the Extended Control Modeenable of this pin. When pin 52 is held at logic low, this pinacts as the DCLK_RST- pin. When in differential DCLK_RSTmode, there is no pin-controlled FSR and the full-scale-rangeis defaulted to the higher VIN input level.
Calibration Delay, Dual Edge Sampling and Serial InterfaceChip Select. In non-extended control mode, this pin functionsas the Calibration Delay select. A logic high or low thenumber of input clock cycles after power up before
calibration begins (See 1.1.1 Calibration). When this pin isfloating or connected to a voltage equal to VA/2, DES (DualEdge Sampling) Mode is selected where the I-channel issampled at twice the input clock rate and the Q-channel isignored. See 1.1.5.1 Dual-Edge Sampling. In extendedcontrol mode, this pin acts as the enable pin for the serialinterface input and the CalDly value becomes \"0\" (shortdelay with no provision for a long power-up calibration delay).
14
FSR/ALT_ECE/DCLK_RST-
127CalDly / DES / SCS1819CLK+CLK-
Differential clock input pins for the ADC. The differential clocksignal must be a.c. coupled to these pins. The input signal issampled on the falling edge of CLK+. See 1.1.2 Acquiringthe Input for a description of acquiring the input and 2.3 THECLOCK INPUTS for an overview of the clock inputs.
10112223
VINI-VINI+VINQ+VINQ−
Analog signal inputs to the ADC. The differential full-scaleinput range of this input is programmable using the FSR pin14 in Non-Extended Control Mode and the Input Full-ScaleVoltage Adjust register in the Extended Control Mode. Referto the VIN specification in the Converter Electrical
Characteristics for the full-scale input range in the Non-Extended Control Mode. Refer to 1.4 REGISTER
DESCRIPTION for the full-scale input range in the ExtendedControl Mode.
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ADC08D1520Pin FunctionsPin No.
Symbol
Equivalent Circuit
Description
Common Mode Voltage. This pin is the common modeoutput in d.c. coupling mode and also serves as the a.c.coupling mode select pin. When d.c. coupling is used at theanalog inputs, the voltage output at this pin is required to bethe common mode input voltage at VIN+ and VIN−. When a.c.coupling is used, this pin should be grounded. This pin iscapable of sourcing or sinking 100 μA. See 2.2 THEANALOG INPUT.
Bandgap output voltage. This pin is capable of sourcing orsinking 100 μA and can drive a load up to 80 pF.
7
VCMO
31
VBG
126CalRun
Calibration Running indication. This pin is at a logic highwhen calibration is running.
32
REXT
External bias resistor connection. Nominal value is 3.3 kΩ(±0.1%) to ground. See 1.1.1 Calibration.
3435Tdiode_PTdiode_N
Temperature Diode Positive (Anode) and Negative
(Cathode). These pins may be used for die temperaturemeasurements, however no specified accuracy is implied orguaranteed. Noise coupling from adjacent output datasignals has been shown to affect temperature
measurements using this feature. See 2.6.2 ThermalManagement.
Extended Control Enable. This pin always enables or
disables Extended Control Mode. When this pin is set logichigh, the Extended Control Mode is inactive and all controlof the device must be through control pins only . When it isset logic low, the Extended Control Mode is active. This pinoverrides the Extended Control Enable signal set using pin14.
DCLK_RST select. This pin selects whether the DCLK isreset using a single-ended or differential signal. When thispin is floating or logic high, the DCLK_RST operation issingle-ended and pin 14 functions as FSR/ALT_ECE. Whenthis pin is logic low, the DCLK_RST operation becomesdifferential with functionality on pin 15 (DCLK_RST+) and pin14 (DCLK_RST-). When in differential DCLK_RST mode,there is no pin-controlled FSR and the full-scale-range isdefaulted to the higher VIN input level. When pin 41 is setlogic low, the Extended Control Mode is active and the Full-Scale Voltage Adjust registers can be programmed.
41ECE52DRST_SEL
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ADC08D1520Pin FunctionsPin No.83 / 7884 / 7785 / 7686 / 75 / 7290 / 7191 / 7092 / 6993 / / 6795 / 6696 / 65100 / 61101 / 60102 / 59103 / 58104 / 57105 / 56106 / 55107 / 111 / 50112 / 49113 / 48114 / 47115 / 46116 / 45117 / 44118 / 43122 / 39123 / 38124 / 37125 / 36
SymbolDI7− / DQ7−DI7+ / DQ7+DI6− / DQ6−DI6+ / DQ6+DI5− / DQ5−DI5+ / DQ5+DI4− / DQ4−DI4+ / DQ4+DI3− / DQ3−DI3+ / DQ3+DI2− / DQ2−DI2+ / DQ2+DI1− / DQ1−DI1+ / DQ1+DI0− / DQ0−DI0+ / DQ0+DId7− / DQd7−DId7+ / DQd7+DId6− / DQd6−DId6+ / DQd6+DId5− / DQd5−DId5+ / DQd5+DId4− / DQd4−DId4+ / DQd4+DId3− / DQd3−DId3+ / DQd3+DId2− / DQd2−DId2+ / DQd2+DId1− / DQd1−DId1+ / DQd1+DId0− / DQd0−DId0+ / DQd0+
Equivalent Circuit
Description
I- and Q-channel LVDS Data Outputs that are not delayed inthe output demultiplexer. Compared with the DId and DQdoutputs, these outputs represent the later time samples.These outputs should always be terminated with a 100Ωdifferential resistor.
In Non-demultiplexed Mode, only these outputs are active.
I- and Q-channel LVDS Data Outputs that are delayed byone CLK cycle in the output demultiplexer. Compared withthe DI and DQ outputs, these outputs represent the earliertime sample. These outputs should always be terminatedwith a 100Ω differential resistor.
In Non-demultiplexed Mode, these outputs are disabled andare high impedance. When disabled, these outputs must beleft floating.
7980OR+/DCLK2+OR-/DCLK2-
Out Of Range, second Data Clock output. When functioningas OR+/-, a differential high at these pins indicates that thedifferential input is out of range (outside the range ±VIN/2 asprogrammed by the FSR pin in Non-extended Control Modeor the Input Full-Scale Voltage Adjust register setting in theExtended Control Mode). This single out of range indicationis for both the I- and Q-channels, unless PDQ is asserted, inwhich case it only applies to the I-channel input. Whenfunctioning as DCLK2+/-, DCLK2 is the exact replica ofDCLK and outputs the same signal at the same rate. Thefunctionality of these pins is selectable in Extended ControlMode only; default is OR+/-.
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ADC08D1520Pin FunctionsPin No.
Symbol
Equivalent Circuit
Description
Data Clock. Differential Clock outputs used to latch theoutput data. Delayed and non-delayed data outputs aresupplied synchronously to this signal. In 1:2 Demux Mode,this signal is at 1/2 the input clock rate in SDR mode and at1/4 the input clock rate in the DDR mode. In the Non-demuxMode, DCLK can only be in DDR mode and is at 1/2 the inputclock rate. By default, the DCLK outputs are not active duringthe termination resistor trim section of the calibration cycle.If a system requires DCLK to run continuously during acalibration cycle, the termination resistor trim portion of thecycle can be disabled by setting the Resistor Trim Disable(RTD) bit to logic high in the Extended Configuration
Register. This disables all subsequent termination resistortrims after the initial trim which occurs during power-oncalibration. This output is not recommended as a systemclock unless the resistor trim is disabled.
8182DCLK-DCLK+
2, 5, 8, 13,16, 17, 20,25, 28, 33,
12840, 51, 62,73, 88, 99,110, 1211, 6, 9, 12,21, 24, 2742, 53, ,74, 87, 97,108, 11963, 98, 109,
120
VA
Analog power supply pins. Bypass these pins to ground.
VDRGND
Output Driver power supply pins. Bypass these pins to DRGND.
Ground return for VA.Ground return for VDR.
No Connection. Make no connection to these pins.
DR GND
NC
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ADC08D1520Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (VA, VDR)Supply Difference VDR - VA
Voltage on Any Input Pin(Except VIN+, VIN- )Voltage on VIN+, VIN-(Maintaining Common Mode)Ground Difference |GND - DR GND|
Input Current at Any Pin (Note 3)Package Input Current (Note 3)Power Dissipation at TA ≤ 85°CESD Susceptibility (Note 4) Human Body Model Machine Model
Charged Device ModelStorage Temperature
2.2V
0V to 100 mV
−0.15V to (VA +0.15V)
-0.15V to 2.5V0V to 100 mV
±25 mA±50 mA
2.35 W
2500V250V1000V
−65°C to +150°C
Operating Ratings
Ambient Temperature Range
(Notes 1, 2)
−40°C ≤ TA ≤ +85°C+1.8V to +2.0V+1.8V to VAVCMO ±50 mV0V to 2.15V(100% duty cycle)
0V to 2.5V(10% duty cycle)0V0V to VA
0.4VP-P to 2.0VP-P
Supply Voltage (VA)
Driver Supply Voltage (VDR)
Analog Input Common Mode VoltageVIN+, VIN- Voltage Range(Maintaining Common Mode)
Ground Difference
(|GND - DR GND|)CLK Pins Voltage RangeDifferential CLK Amplitude
Package Thermal Resistance
Package128-Lead,
Exposed Pad LQFP
θJA26°C / W
θJCTop ofPackage10°C / W
θJCThermalPad2.8°C / W
Soldering process must comply with NationalSemiconductor’s Reflow Temperature Profile specifications.Refer to www.national.com/packaging. (Note 5)
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating;Non-extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2Demultiplex Mode; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unlessotherwise noted. (Notes 6, 7, 16)Symbol
Parameter
Conditions
Typical(Note 8)
Limits(Note 8)
Units(Limits)
STATIC CONVERTER CHARACTERISTICSINLDNL VOFFVOFF_ADJPFSENFSEFS_ADJFPBWC.E.R. ENOBSINAD
Integral Non-Linearity(Best fit)
Differential Non-LinearityResolution with No MissingCodesOffset Error
Positive Full-Scale ErrorNegative Full-Scale ErrorFull-Scale Adjustment RangeFull Power BandwidthCode Error RateGain Flatness
Effective Number of Bits
DC Coupled, 1 MHz Sine Wave Over-ranged
DC Coupled, 1 MHz Sine Wave Over-ranged (Note 9)(Note 9)
Extended Control ModeNon-DES Mode
d.c. to 748 MHzd.c. to 1.5 GHz
fIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dB
±0.3±0.15 −0.75±45 ±202.010−18±0.5±1.07.47.446.6.4
±0.9±0.68 ±25±25±15 6.8 42.5
LSB (max)LSB (max)
BitsLSBmVmV (max)mV (max)%FSGHzError/Sample
dBFSdBFSBits (min)BitsdB (min)dB
Input Offset Adjustment RangeExtended Control Mode
1:2 DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ
Signal-to-Noise Plus DistortionfIN = 373 MHz, VIN = FSR − 0.5 dBRatiofIN = 748 MHz, VIN = FSR − 0.5 dB
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ADC08D1520SymbolSNRTHD2nd Harm3rd HarmSFDRIMD
Parameter
Signal-to-Noise RatioTotal Harmonic DistortionSecond Harmonic DistortionThird Harmonic DistortionSpurious-Free Dynamic RangeIntermodulation DistortionOut of Range Output Code
Conditions
fIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 373 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN1 = 365 MHz, VIN = FSR − 7 dBfIN2 = 375 MHz, VIN = FSR − 7 dB(VIN+) − (VIN−) > + Full Scale(VIN+) − (VIN−) < − Full ScalefIN = 248 MHz, VIN = FSR − 0.5 dBfIN = 498 MHz, VIN = FSR − 0.5 dB
Typical(Note 8)46.847−58−55−65−59−58−585855−50 7.37.345.745.746-57-57-63-63--57571.37.04446.3−47−55−47
Limits(Note 8)44.0 -47.5
Units(Limits)dB (min)dBdB (max)dBdBdBdBdB
47.5 2550
dB (min)dBdB BitsBitsdBdBdBdBdBdBdBdBdBdBdBdBGHzBitsdBdBdBdBdB
NON-DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1 GHZENOBSINADSNRTHD2nd Harm3rd HarmSFDR
Effective Number of Bits
Signal to Noise Plus DistortionfIN = 248 MHz, VIN = FSR − 0.5 dBRatiofIN = 498 MHz, VIN = FSR − 0.5 dBSignal to Noise RatioTotal Harmonic DistortionSecond Harmonic DistortionThird Harmonic DistortionSpurious Free Dynamic Range
fIN = 248 MHz, VIN = FSR − 0.5 dBfIN = 498 MHz, VIN = FSR − 0.5 dBfIN = 248 MHz, VIN = FSR − 0.5 dBfIN = 498 MHz, VIN = FSR − 0.5 dBfIN = 248 MHz, VIN = FSR − 0.5 dBfIN = 498 MHz, VIN = FSR − 0.5 dBfIN = 248 MHz, VIN = FSR − 0.5 dBfIN = 498 MHz, VIN = FSR − 0.5 dBfIN = 248 MHz, VIN = FSR − 0.5 dBfIN = 498 MHz, VIN = FSR − 0.5 dBDES Mode
fIN = 748 MHz, VIN = FSR − 0.5 dB
1:4 DEMUX DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZFPBWENOBSINADSNRTHD2nd Harm3rd HarmSFDR
Full Power BandwidthEffective Number of Bits
Signal to Noise Plus Distortion
fIN = 748 MHz, VIN = FSR − 0.5 dB
Ratio
Signal to Noise RatioTotal Harmonic DistortionSecond Harmonic DistortionThird Harmonic Distortion
fIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dBfIN = 748 MHz, VIN = FSR − 0.5 dB
Spurious Free Dynamic RangefIN = 748 MHz, VIN = FSR − 0.5 dB
590730800940VCMO − 0.05VCMO + 0.05
dBmVP-P (min)mVP-P (max)mVP-P (min)mVP-P (max)V (min)V (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
Full Scale Analog DifferentialInput Range
FSR pin 14 LowFSR pin 14 High
650870VCMO
VIN
VCMI
Common Mode Input Voltage
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ADC08D1520SymbolParameter
Analog Input Capacitance,Normal operation(Notes 10, 11)
Analog Input Capacitance,DES Mode (Notes 10, 11)
Differential
Conditions
Typical(Note 8)0.021.60.082.2100
Limits(Note 8)
941060.951.45 801.201.33 80
Units(Limits)pFpFpFpFΩ (min)Ω (max)V (min)V (max)ppm/°CVVpFV (min)V (max)ppm/°CpF
CIN
Each input pin to groundDifferential
Each input pin to ground
RIN
Differential Input Resistance
ANALOG OUTPUT CHARACTERISTICSVCMOTC VCMOVCMO_LVLCLOAD VCMOVBGTC VBGCLOAD VBG
Common Mode Output VoltageICMO = ±100 µACommon Mode Output Voltage
TA = −40°C to +85°C
Temperature Coefficient
VCMO input threshold to set D.C.VA = 1.8VCoupling modeVA = 2.0VMaximum VCMO LoadCapacitance
Bandgap Reference OutputVoltage
Bandgap Reference VoltageTemperature Coefficient
IBG = ±100 µATA = −40°C to +85°C,IBG = ±100 µA
1.261180.600.66 1.2628
Maximum Bandgap Reference
load CapacitanceOffset Match
Positive Full-Scale MatchNegative Full-Scale MatchPhase Matching (I, Q)Crosstalk from I-channel(Aggressor) to Q-channel(Victim)
Crosstalk from Q-channel(Aggressor) to I-channel(Victim)
Zero offset selected in Control RegisterZero offset selected in Control RegisterfIN = 1.5 GHz
Aggressor = 867 MHz F.S.Victim = 100 MHz F.S.Aggressor = 867 MHz F.S.Victim = 100 MHz F.S.
CHANNEL-TO-CHANNEL CHARACTERISTICS X-TALK
111< 1−65
LSBLSBLSBDegreedB
X-TALK−65 dB
LVDS CLK INPUT CHARACTERISTICS (Typical specs also apply to DCLK_RST)
Sine Wave Clock
VID
Differential Clock Input Level
Square Wave Clock
VOSICIN
Input Offset VoltageInput Capacitance(Notes 10, 11)
Differential
Each input to ground
OutV, DCLK_RST, PD, PDQ, CAL, ECE,DRST_SEL
OutEdge, FSR, CalDly
VILCIN
Logic Low Input VoltageInput Capacitance(Notes 11, 13)
OutV, DCLK_RST, PD, PDQ, CALOutEdge, FSR, CalDly, ECE, DRST_SELEach input to ground
0.61.20.021.50.6
0.42.00.42.0
VP-P (min)VP-P (max)VP-P (min)VP-P (max)
VpFpF
DIGITAL CONTROL PIN CHARACTERISTICSVIH
Logic High Input Voltage
1.2
0.69 x VA0.79 x VA0.28 x VA0.21 x VA
V (min)V (min)V (max)V (max)pF
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ADC08D1520SymbolParameterConditions
Typical(Note 8)Limits(Note 8)480950320720 1.50.3 9300 803530 305166 212120 2.351.53 1.921.235
Units(Limits)mVP-P (min)mVP-P (max)mVP-P (min)mVP-P (max)
mVmVmVmVmAOhmsVV mA (max)mA (max)mA mA (max)mA (max)mA mA (max)mA (max)mA mA (max)mA (max)mA W (max)W (max)mWW (max)W (max)mWdB
DIGITAL OUTPUT CHARACTERISTICS
LVDS Differential OutputVoltage
Measured differentially, OutV = VA,VBG = Floating (Note 15)
Measured differentially, OutV = GND, VBG= Floating (Note 15)
740560±18001175±1±41001.650.15 8185611.9 71241.5 2251230.074 13683.50.047 2.01.33.8 1.61.042.76-30
VOD
ΔVO DIFFVOSΔVOSIOSZOVOHVOL
Change in LVDS Output Swing
Between Logic LevelsOutput Offset VoltageSee Figure 1
VBG = FloatingVBG = VA (Note 15)
Output Offset Voltage Change
Between Logic LevelsOutput Short Circuit CurrentDifferential Output ImpedanceCalRun H level outputCalRun L level output
Output+ and Output−connected to 0.8V
IOH = −400 µA (Note 12)IOH = 400 µA (Note 12)
1:2 Demux Mode; fCLK = 1.5 GHzPD = PDQ = Low
PD = Low, PDQ = HighPD = PDQ = High
Non-demux Mode; fCLK = 1.0 GHzPD = PDQ = Low
PD = Low, PDQ = HighPD = PDQ = High
1:2 Demux Mode; fCLK = 1.5 GHzPD = PDQ = Low
PD = Low, PDQ = HighPD = PDQ = High
Non-demux Mode; fCLK = 1.0 GHzPD = PDQ = Low
PD = Low, PDQ = HighPD = PDQ = High
1:2 Demux Mode; fCLK = 1.5 GHzPD = PDQ = Low
PD = Low, PDQ = HighPD = PDQ = High
Non-demux Mode; fCLK = 1.0 GHzPD = PDQ = Low
PD = Low, PDQ = HighPD = PDQ = High
Change in Full Scale Error with change inVA from 1.8V to 2.0V
POWER SUPPLY CHARACTERISTICS (NON-DES MODE)
IA
Analog Supply Current
IDR
Output Driver Supply Current
PD
Power Consumption
PSRR1
D.C. Power Supply RejectionRatio
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ADC08D1520SymbolParameterConditions
Typical(Note 8)1.7 20050050333333509030 150150
Limits(Note 8)1.51.0 20801331334555
Units(Limits)GHz (max)GHz (max)MHzMHz% (min)% (max)ps (min)ps (min)% (min)% (max)pspsInput ClockCycles (min)
psps
A.C. ELECTRICAL CHARACTERISTICSfCLK (max)
Maximum Input ClockFrequency
Minimum Input ClockFrequency
Input Clock Duty CycleInput Clock Low TimeInput Clock High TimeDCLK Duty CycleSetup Time DCLK_RST±Hold Time DCLK_RST±Pulse Width DCLK_RST±Differential Low-to-HighTransition TimeDifferential High-to-LowTransition Time
DCLK-to-Data Output SkewData-to-DCLK Set-Up TimeDCLK-to-Data Hold TimeSampling (Aperture) DelayAperture Jitter
Input Clock-to Data OutputDelay (in addition to PipelineDelay)
Demux Mode (DES or Non-DES Mode)Non-Demux Mode (DES or Non-DESMode)
1:2 Demux Non-DES Mode1:4 Demux DES ModefCLK(min) ≤ fCLK ≤ 1.5 GHz(Note 12)(Note 11)(Note 11)(Note 11)(Note 12)(Note 12)(Note 11)
10% to 90%, CL = 2.5 pF10% to 90%, CL = 2.5 pF
50% of DCLK transition to 50% of Datatransition, SDR Mode
and DDR Mode, 0° DCLK (Note 11)DDR Mode, 90° DCLK (Note 11)DDR Mode, 90° DCLK (Note 11)Input CLK+ Fall to Acquisition of Data
50% of Input Clock transition to 50% of DatatransitionDI Outputs
DId Outputs
Pipeline Delay (Latency) in 1:2
DQ OutputsDemux Mode
(Notes 11, 14)
DQd Outputs
Pipeline Delay (Latency) inNon-Demux Mode(Notes 11, 14)
Over Range Recovery TimePD low to Rated AccuracyConversion (Wake-Up Time)Serial Clock FrequencySerial Data to Serial ClockRising Setup TimeSerial Data to Serial ClockRising Hold Time
DI OutputsDQ Outputs
Non-DES ModeDES Mode
15001152.512.5
Non-DES ModeDES ModeNon-DES ModeDES Mode
fCLK (min) tCLtCH tSRtHRtPWRtLHTtHLTtOSKtSUtHtADtAJtOD
4
±504005601.60.44.0
ps (max)psps
13141313.51414.5131313.5
nsps (rms)ns
Input ClockCycles
Input ClockCyclesInput ClockCycle
nsµsMHzns (min)ns (min)ns
tWUfSCLKtSSUtSHtSCS
Differential VIN step from ±1.2V to 0V to getaccurate conversionNon-DES Mode (Note 11)DES Mode (Note 11)(Note 11)(Note 11)(Note 11)
CS to Serial Clock Rising Setup
Time
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ADC08D1520SymboltHCS tCALtCAL_LtCAL_H
Parameter
CS to Serial Clock Falling Hold
Time
Serial Clock Low TimeSerial Clock High TimeCalibration Cycle TimeCAL Pin Low TimeCAL Pin High Time
Conditions
Typical(Note 8)1.5 1.4 x 106
Limits(Note 8)
3030 12801280
Units(Limits)nsns (min)ns (min)Clock CyclesClock Cycles
(min)Clock Cycles
(min)Clock Cycles
(max)Clock Cycles
(max)
See Figure 10 (Note 11)See Figure 10 (Note 11)CalDly = Low
See 1.1.1 Calibration, Figure 10,(Note 11)
CalDly = High
See 1.1.1 Calibration, Figure 10,(Note 11)
226
tCalDly
Calibration delay determinedby CalDly (pin 127)
232
Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute MaximumRatings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specificationsand test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristicsmay degrade when the device is not operated under the listed test conditions.
Note 2:All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3:When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA totwo. This limit is not placed upon the power, ground and digital output pins.
Note 4:Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Charged devicemodel simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.Note 5:Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 6:The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
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Note 7:To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,achieving rated performance requires that the backside exposed pad be well grounded.
Note 8:Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing QualityLevel).
Note 9:Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, seeSpecification Definitions for Gain Error.
Note 10:The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin toground are isolated from the die capacitances by lead and bond wire inductances.Note 11:This parameter is guaranteed by design and is not tested in production.
Note 12:This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13:The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the diecapacitances by lead and bond wire inductances.
Note 14:The ADC08D1520 has two LVDS output buses, each of which clocks data out at one half the sample rate. The second bus (D0 through D7) has apipeline latency that is one clock cycle less than the latency of the first bus (Dd0 through Dd7).
Note 15:Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to thesupply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).Note 16:The maximum clock frequency for Non-Demux Mode is 1 GHz.
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ADC08D1520Specification Definitions
APERTURE (SAMPLING) DELAY is the amount of delay,measured from the sampling edge of the CLK input, afterwhich the signal present at the input pin is sampled inside thedevice.
APERTURE JITTER (tAJ) is the variation in aperture delayfrom sample to sample. Aperture jitter shows up as inputnoise.
CODE ERROR RATE (C.E.R.) is the probability of error andis defined as the probable number of word errors on the ADCoutput per unit of time divided by the number of words seenin that amount of time. A C.E.R. of 10-18 corresponds to astatistical error in one word about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clockwaveform is at a logic high to the total time of one clock period.DIFFERENTIAL NON-LINEARITY (DNL) is the measure ofthe maximum deviation from the ideal step size of 1 LSB.Measured at sample rate = 500 MSPS with a 1MHz input sinewave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVEBITS) is another method of specifying Signal-to-Noise andDistortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to a per-fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of thefrequency at which the reconstructed output fundamentaldrops 3 dB below its low frequency value for a full-scale input.GAIN ERROR is the deviation from the ideal slope of thetransfer function. It can be calculated from Offset and Full-Scale Errors:
Positive Gain Error = Offset Error − Positive Full-ScaleError
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Negative Gain Error = −(Offset Error − Negative Full-Scale Error)
Gain Error = Negative Full-Scale Error − Positive Full-Scale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL) is a measure of worstcase deviation of the ADC transfer function from an idealstraight line drawn through the ADC transfer function. Thedeviation of any given code from this straight line is measuredfrom the center of that code value step. The best fit methodis used.
INTERMODULATION DISTORTION (IMD) is the creation ofadditional spectral components as a result of two sinusoidalfrequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and thirdorder intermodulation products to the power in one of theoriginal frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-est value or weight of all bits. This value is
VFS / 2N
where VFS is the differential full-scale amplitude VIN as set bythe FSR input and \"N\" is the ADC resolution in bits, which is8 for the ADC08D1520.
LOW VOLTAGE DFFERENTAL SGNALNG (LVDS)DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is twotimes the absolute value of the difference between the VD+and VD - signals; each measured with respect to Ground.
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FIGURE 1. LVDS Output Signal Levels
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpointbetween the D+ and D- pins output voltage with respect toground; i.e., [(VD+) +( VD-)]/2. See Figure 1.
MISSING CODES are those output codes that are skippedand will never appear at the ADC outputs. These codes can-not be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largestvalue or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure ofhow far the first code transition is from the ideal 1/2 LSB abovea differential −VIN/2 with the FSR pin low. For the AD-C08D1520 the reference voltage is assumed to be ideal, sothis error is a combination of full-scale error and referencevoltage error.
OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input.Offset Error = Actual Input causing average of 8k samples toresult in an average code of 127.5.
OUTPUT DELAY (tOD) is the time delay (in addition toPipeline Delay) after the falling edge of CLK+ before the dataupdate is present at the output pins.
OVER-RANGE RECOVERY TIME is the time required afterthe differential input voltages goes from ±1.2V to 0V for theconverter to recover and make a conversion with its rated ac-curacy.
PIPELINE DELAY (LATENCY) is the number of input clockcycles between initiation of conversion and when that data ispresented to the output driver stage. New data is available atevery clock cycle, but the data lags the conversion by thePipeline Delay plus the tOD.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure ofhow far the last code transition is from the ideal 1-1/2 LSBbelow a differential +VIN/2. For the ADC08D1520 the refer-ence voltage is assumed to be ideal, so this error is a combi-nation of full-scale error and reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) can be oneof two specifications. PSRR1 (D.C. PSRR) is the ratio of thechange in full-scale error that results from a power supplyvoltage change from 1.8V to 2.0V. PSRR2 (A.C. PSRR) is ameasure of how well an a.c. signal riding upon the powersupply is rejected from the output and is measured with a 248MHz, 50 mVP-P signal riding upon the power supply. It is theratio of the output amplitude of that signal at the output to itsamplitude on the power supply pin. PSRR is expressed in dB.SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed indB, of the rms value of the input signal at the output to the rmsvalue of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c.
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ADC08D1520SGNAL TO NOSE PLUS DSTORTON (S/(N+D) orSINAD) is the ratio, expressed in dB, of the rms value of theinput signal at the output to the rms value of all of the otherspectral components below half the input clock frequency, in-cluding harmonics but excluding d.c.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ-ence, expressed in dB, between the rms values of the inputsignal at the output and the peak spurious signal, where aspurious signal is any signal present in the output spectrumthat is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio ex-pressed in dB, of the rms total of the first nine harmonic levelsat the output to the level of the fundamental at the output. THDis calculated as
where Af1 is the RMS power of the fundamental (output) fre-quency and Af2 through Af10 are the RMS power of the first 9harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2nd Harm) is the differ-ence, expressed in dB, between the RMS power in the inputfrequency seen at the output and the power in its 2nd har-monic level at the output.
– Third Harmonic Distortion (3rd Harm) is the differenceexpressed in dB between the RMS power in the input fre-quency seen at the output and the power in its 3rd harmoniclevel at the output.
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ADC08D1520Transfer Characteristic
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FIGURE 2. Input / Output Transfer Characteristic
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ADC08D1520Timing Diagrams
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FIGURE 3. SDR Clocking in 1:2 Demultiplexed Non-DES Mode
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FIGURE 4. DDR Clocking in 1:2 Demultiplexed Non-DES Mode
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ADC08D152020193160
FIGURE 5. DDR Clocking in Non-Demultiplexed Non-DES Mode
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FIGURE 6. Serial Interface Timing
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FIGURE 7. Clock Reset Timing in DDR Mode
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ADC08D152020193123
FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE Low
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FIGURE 9. Clock Reset Timing in SDR Mode with OUTEDGE High
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FIGURE 10. Power-on and On-Command Calibration Timing
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ADC08D1520VA = VDR = 1.9V, fCLK = 1500 MHz, fIN = 748 MHz, TA= 25°C, I
channel, 1:2 Demux Mode (1:1 Demux Mode has similar performance), unless otherwise stated.
INL vs. CODE
INL vs. TEMPERATURE
Typical Performance Characteristics
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DNL vs. CODEDNL vs. TEMPERATURE
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POWER CONSUMPTION vs. CLOCK FREQUENCYENOB vs. TEMPERATURE
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ADC08D1520ENOB vs. SUPPLY VOLTAGEENOB vs. CLOCK FREQUENCY
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ENOB vs. INPUT FREQUENCYSNR vs. TEMPERATURE
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SNR vs. SUPPLY VOLTAGESNR vs. CLOCK FREQUENCY
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ADC08D1520SNR vs. INPUT FREQUENCYTHD vs. TEMPERATURE
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THD vs. SUPPLY VOLTAGETHD vs. CLOCK FREQUENCY
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THD vs. INPUT FREQUENCYSFDR vs. TEMPERATURE
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ADC08D1520SFDR vs. SUPPLY VOLTAGESFDR vs. CLOCK FREQUENCY
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SFDR vs. INPUT FREQUENCYSpectral Response at FIN = 373 MHz
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Spectral Response at FIN = 748 MHzCROSSTALK vs. SOURCE FREQUENCY
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ADC08D1520FULL POWER BANDWIDTH (NON-DES MODE)GAIN STABILITY vs. DIE TEMPERATURE
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ADC08D15201.0 Functional Description
The ADC08D1520 is a versatile A/D Converter with an inno-vative architecture permitting very high speed operation. Thecontrols available ease the application of the device to circuitsolutions. Optimum performance requires adherence to theprovisions discussed here and in the Applications InformationSection.
While it is generally poor practice to allow an active pin to float,pins 4, 14, 52 and 127 of the ADC08D1520 are designed tobe left floating without jeopardy. In all discussions for pins 4,14, and 127, whenever a function is called by allowing thesecontrol pins to float, connecting that pin to a potential of onehalf the VA supply voltage will have the same effect as allow-ing it to float.
1.1 OVERVIEW
The ADC08D1520 uses a calibrated folding and interpolatingarchitecture that achieves 7.4 effective bits. The use of foldingamplifiers greatly reduces the number of comparators andpower consumption. Interpolation reduces the number offront-end amplifiers required, minimizing the load on the inputsignal and further reducing power requirements. In additionto correcting other non-idealities, on-chip calibration reducesthe INL bow often seen with folding architectures. The resultis an extremely fast, high performance, low power converter.The analog input signal that is within the converter's inputvoltage range is digitized to eight bits at speeds of 200 MSPSto 1.7 GSPS, typical. Differential input voltages below nega-tive full-scale will cause the output word to consist of allzeroes. Differential input voltages above positive full-scalewill cause the output word to consist of all ones. Either ofthese conditions at either the I- or Q-channel will cause theOut of Range (OR) output to be activated. This single ORoutput indicates when the output code from one or both of thechannels is below negative full scale or above positive fullscale. When PDQ is asserted, the OR indication applies tothe I channel only.
For Non-DES Modes, each converter has a selectable outputdemultiplexer which feeds two LVDS buses. If the 1:2 DemuxMode is selected, the output data rate is reduced to half theinput sample rate on each bus. When Non-demux Mode isselected, the output data rate on channels DI and DQ are atthe same rate as the input sample clock.
The output levels may be selected to be normal or reduced.Using reduced levels saves power but could result in erro-neous data capture of some or all of the bits, especially athigher sample rates and in marginally designed systems.1.1.1 Calibration
A calibration is performed upon power-up and can also beinvoked by the user upon command. Calibration trims the100Ω analog input differential termination resistor and mini-mizes full-scale error, offset error, DNL and INL, resulting inmaximizing SNR, THD, SINAD (SNDR) and ENOB. Internalbias currents are also set during the calibration process. Allof this is true whether the calibration is performed upon powerup or is performed upon command. Running the calibration isrequired for proper operation and to obtain the ADC's speci-fied performance. In addition to the requirement to be run atpower-up, an on-command calibration must be run wheneverthe sense of the FSR pin is changed. For best performance,it is recommend that an on-command calibration be run 20seconds or more after application of power and whenever theoperating temperature changes significantly, relative to thespecific system performance requirements. See 2.4.2.2 On-Command Calibration for more information. Calibration can-www.national.com
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not be initiated or run while the device is in the power-downmode. See 1.1.7 Power Down for information on the interac-tion between Power Down and Calibration.
In normal operation, calibration is performed just after appli-cation of power and whenever a valid calibration command isgiven, which may be accomplished one of two ways, via theCAL pin (30) or the Calibration register (Addr: 0h, Bit 15). Thecalibration command is achieved by holding the CAL pin lowfor at least tCAL_L clock cycles, and then holding it high for atleast another tCAL_H clock cycles, as defined in the ConverterElectrical Characteristics. The time taken by the calibrationprocedure is specified as tCALin Converter Electrical Charac-teristics. Holding the CAL pin high upon power up will preventthe calibration process from running until the CAL pin expe-riences the above-mentioned tCAL_L clock cycles followed bytCAL_H clock cycles.
CalDly (pin 127) is used to select one of two delay times thattake place from the application of power to the start of cali-bration. This calibration delay time is dependent on the settingof the CalDly pin and is specified as tCalDly in the ConverterElectrical Characteristics. These delay values allow the pow-er supply to come up and stabilize before calibration takesplace. If the PD pin is high upon power-up, the calibration de-lay counter will be disabled until the PD pin is brought low.Therefore, holding the PD pin high during power up will furtherdelay the start of the power-up calibration cycle. The bestsetting of the CalDly pin depends upon the power-on settlingtime of the power supply.
1.1.2 Acquiring the Input
In 1:2 Demux Non-DES Mode, data is acquired at the fallingedge of CLK+ (pin 18) and the digital equivalent of that datais available at the digital outputs 13 input clock cycles later forthe DI and DQ output buses and 14 input clock cycles laterfor the DId and DQd output buses. See Pipeline Delay in theConverter Electrical Characteristics. There is an additionalinternal delay called tOD before the data is available at theoutputs. See the Timing Diagrams. The ADC08D1520 willconvert as long as the input clock signal is present. The fullydifferential comparator design and the innovative design ofthe sample-and-hold amplifier, together with self calibration,enables a very flat SINAD/ENOB response beyond 1.5 GHz.The ADC08D1520 output data signaling is LVDS and the out-put format is offset binary.
1.1.3 Control Modes
Much of the user control can be accomplished with severalcontrol pins that are provided. Examples include initiation ofthe calibration cycle, power down mode and full scale rangesetting. However, the ADC08D1520 also provides an Extend-ed Control Mode whereby a serial interface is used to accessregister-based control of several advanced features. The Ex-tended Control Mode is not intended to be enabled anddisabled dynamically. Rather, the user is expected to employeither the Non-extended Control Mode or the Extended Con-trol Mode at all times. When the device is in the ExtendedControl Mode, pin-based control of several features is re-placed with register-based control and those pin-based con-trols are disabled. These pins are OutV (pin 3), OutEdge/DDR(pin 4), FSR (pin 14) and CalDly/DES (pin 127). See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for detailson the Extended Control Mode.
1.1.4 The Analog Inputs
The ADC08D1520 must be driven with a differential input sig-nal. Operation with a single-ended signal is not recommend-ed. It is important that the inputs either be a.c. coupled to the
ADC08D1520inputs with the VCMO (pin 7) grounded, or d.c. coupled with theVCMO pin left floating. An input common mode voltage equalto the VCMO output must be provided as the common modeinput voltage to VIN+ and VIN- when d.c. coupling is used.Two full-scale range settings are provided via pin 14 (FSR).In Non-extended Control Mode, a logic high on pin 14 causesan input full-scale range setting of a normal VIN input level,while a logic low on pin 14 causes an input full-scale rangesetting of a reduced VIN input level. The full-scale range set-ting operates on both ADCs.
In the Extended Control Mode, programming the Input Full-Scale Voltage Adjust register allows the input full-scale rangeto be adjusted as described in 1.4 REGISTER DESCRIP-TION and 2.2 THE ANALOG INPUT.
1.1.5 Clocking
The ADC08D1520 must be driven with an a.c. coupled, dif-ferential clock signal. 2.3 THE CLOCK INPUTS describes theuse of the clock input pins. A differential LVDS output clock isavailable for use in latching the ADC output data into whateverdevice is used to receive the data.
The ADC08D1520 offers output clocking options: two of theseoptions are Single Data Rate (SDR) and Double Data Rate(DDR). In SDR mode, the user has a choice of which DataClock (DCLK) edge, rising or falling, the output data transi-tions on.
The ADC08D1520 also has the option to use a duty cyclecorrected clock receiver as part of the input clock circuit. Thisfeature is enabled by default and provides improved ADCclocking, especially in the Dual-Edge Sampling (DES) Mode.This circuitry allows the ADC to be clocked with a signalsource having a duty cycle ratio of 20%/80% (worst case) forboth the Non-DES and the DES Modes.
1.1.5.1 Dual-Edge Sampling
The Dual-Edge Sampling (DES) Mode allows either of theADC08D1520's inputs (I- or Q-channel) to be sampled by bothADCs. One ADC samples the input on the rising edge of theinput clock and the other ADC samples the same input on thefalling edge of the input clock. A single input is thus sampledtwice per input clock cycle, resulting in an overall sample rateof twice the input clock frequency, or 3 GSPS with a 1.5 GHzinput clock.
In this mode, the outputs must be carefully interleaved to re-construct the sampled signal. If the device is programmed intothe 1:4 Demux DES Mode, the data is effectively demulti-plexed by 1:4. If the input clock is 1.5 GHz, the effectivesampling rate is doubled to 3 GSPS and each of the 4 outputbuses has an output rate of 750 MHz. All data is available inparallel. To properly reconstruct the sampled waveform, thefour bytes of parallel data that are output with each clock arein the following sampling order, from the earliest to the latest,and must be interleaved as such: DQd, DId, DQ, DI. Table 1indicates what the outputs represent for the various samplingpossibilities. If the device is programmed into the Non-demuxDES Mode, two bytes of parallel data are output with eachedge of the clock in the following sampling order, from theearliest to the latest: DQ, DI. See Table 2.
In the Non-extended Control and DES Mode of operation,only the I-channel can be sampled. In the Extended ControlMode of operation, the user can select which input is sampled.The ADC08D1520 also includes an automatic clock phasebackground adjustment in DES Mode to automatically andcontinuously adjust the clock phase of the I- and Q-channels.This feature removes the need to adjust the clock phase set-ting manually and provides optimal DES Mode performance.
TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**
Data Outputs(Always sourced withrespect to fall of DCLK+)
DI
Dual-Edge Sampling (DES) Mode
Non-DES Sampling Mode
I-Channel SelectedI-channel sampled with fallof CLK,
13 cycles earlier.
I-channel sampled with fallof CLK,
14 cycles earlier.
Q-Channel Selected *Q-channel sampled with fallof CLK,
13 cycles earlier.
Q-channel sampled with fallof CLK,
14 cycles earlier.
I-channel sampled with fall of CLK,13 cycles earlier.
I-channel sampled with fall of CLK,14 cycles earlier.
DId
DQ
I-channel sampled with riseQ-channel sampled with rise
Q-channel sampled with fall of CLK,
of CLK,of CLK,
13 cycles earlier.
13.5 cycles earlier.13.5 cycles earlier.I-channel sampled with riseQ-channel sampled with rise
Q-channel sampled with fall of CLK,
of CLK,of CLK,
14 cycles earlier.
14.5 cycles earlier.14.5 cycles earlier.
DQd
* Note that, in DES Mode and Non-extended Control Mode, only the I-channel is sampled. In DES Mode and Extended Control Mode, the I- or Q-channel can be
sampled.
** Note that, in the Non-demux Mode (DES and Non-DES Mode), the DId and DQd outputs are disabled and are high impedance.
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ADC08D1520TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demux Mode
Data Outputs(Always sourced withrespect to fall of DCLK+)
DI
Dual-Edge Sampling (DES) Mode
Non-DES Sampling Mode
I-Channel SelectedI-channel sampled with fallof CLK,
14 cycles earlier.No output;
high impedance.
Q-Channel SelectedQ-channel sampled with fallof CLK,
13.5 cycles earlier.No output;
high impedance.
I-channel sampled with fall of CLK,14 cycles earlier.No output;
high impedance.
DId
DQ
I-channel sampled with riseQ-channel sampled with rise
Q-channel sampled with fall of CLK,
of CLK,of CLK,
13.5 cycles earlier.
13.5 cycles earlier.13.5 cycles earlier.No output;
high impedance.
No output;
high impedance.
No output;
high impedance.
DQd
1.1.5.2 OutEdge and Demultiplex Control Setting
To help ease data capture in the Single Data Rate (SDR)mode, the output data may be caused to transition on eitherthe positive or the negative edge of the output data clock(DCLK). In the Non-extended Control Mode, this is selectedby OutEdge (pin 4). A logic high on the OutEdge input pincauses the output data to transition on the rising edge ofDCLK+, while a logic low causes the output to transition onthe falling edge of DCLK+. See 2.4.3 Output Edge Synchro-nization. When in the Extended Control Mode, the OutEdgeis selected using the OED bit in the Configuration Register.This bit has two functions. In the SDR mode, the bit functionsas OutEdge and selects the DCLK edge with which the datatransitions. In the Double Data Rate (DDR) mode, this bit se-lects whether the device is in Non-demux or Demux Mode. Inthe DDR case, the DCLK has a 0° phase relationship with theoutput data, independent of the demultiplexer selection. For1:2 Demux DDR 0° Mode, there are four, as opposed to threecycles of CLK delay from the deassertion of DCLK_RST tothe Synchronizing Edge. See 1.5 MULTIPLE ADC SYN-CHRONIZATION for more information.
1.1.5.3 Double Data Rate and Single Data Rate
A choice of Single Data Rate (SDR) or Double Data Rate(DDR) output is offered. With SDR, the output clock (DCLK)frequency is the same as the data rate of the two output bus-es. With DDR, the DCLK frequency is half the data rate anddata is sent to the outputs on both edges of DCLK. DDRclocking is enabled in Non-extended Control Mode by allow-ing pin 4 to float or by biasing it to half the supply.
1.1.5.4 Clocking Summary
The chip may be in one of four modes, depending on the Dual-Edge Sampling (DES) selection and the demultiplex selec-tion. For the DES selection, there are two possibilities: Non-DES Mode and DES Mode. In Non-DES Mode, each of thechannels (I-channel and Q-channel) functions independently,i.e. the chip is a dual 1.5 GSPS A/D converter. In DES Mode,the I- and Q-channels are interleaved and function togetheras one 3.0 GSPS A/D converter. For the demultiplex selec-tion, there are also two possibilities: Demux Mode and Non-Demux Mode. The I-channel has two 8-bit output bussesassociated with it: DI and DId. The Q-channel also has two 8-bit output busses associated with it: DQ and DQd. In DemuxMode, the channel is demultiplexed by 1:2. In Non-DemuxMode, the channel is not demultiplexed. Note that Non-De-mux Mode is also sometimes referred to as 1:1 Demux Mode.For example, if the I-channel was in Non-Demux Mode, thecorresponding digital output data would be available on only
the DI bus. If the I-channel was in Demux Mode, the corre-sponding digital output data would be available on both theDI and DId busses, but at half the rate of Non-Demux Mode.Given that there are two DES Mode selections (DES Modeand Non-DES Mode) and two demultiplex selections (DemuxMode and Non-Demux Mode), this yields a total of four pos-sible modes: (1) Non-Demux Non-DES Mode, (2) Non-De-mux DES Mode, (3) 1:2 Demux Non-DES Mode, and (4) 1:4Demux DES Mode. The following is a brief explanation of theterms and modes:
1.Non-Demux Non-DES Mode: This mode is when the chip
is in Non-Demux Mode and Non-DES Mode. The I- andQ- channels function independently of one another. Thedigital output data is available for the I-channel on DI, andfor the Q-channel on DQ.
2.Non-Demux DES Mode: This mode is when the chip is
in Non-Demux Mode and DES Mode. The I- and Q-channels are interleaved and function together as onechannel. The digital output data is available on the DI andDQ busses because although the chip is in Non-DemuxMode, both I- and Q-channels are functioning andpassing data.
3.1:2 Demux Non-DES Mode: This mode is when the chip
is in Demux Mode and Non-DES Mode. The I- and Q-channels function independently of one another. Thedigital output data is available for the I-channel on DI andDId, and for the Q-channel on DQ and DQd. This isbecause each channel (I-channel and Q-channel) isproviding digital data in a demultiplexed manner.
4.1:4 Demux DES Mode: This mode is when the chip is in
Demux Mode and DES Mode. The I- and Q- channelsare interleaved and function together as one channel.The digital output data is available on the DI, DId, DQ andDQd busses because although the chip is in DemuxMode, both I- and Q-channels are functioning and
passing data. To avoid confusion, this mode is labeled1:4 because the analog input signal is provided on onechannel and the digital output data is provided on fourbusses.
The choice of Dual Data Rate (DDR) and Single Data Rate(SDR) will only affect the speed of the output Data Clock(DCLK). Once the DES Modes and Demux Modes have beenchosen, the data output rate is also fixed. In the case of SDR,the DCLK runs at the same rate as the output data; outputdata may transition with either the rising or falling edge ofDCLK. In the case of DDR, the DCLK runs at half the rate ofthe output data; the output data transitions on both rising andfalling edges of the DCLK.
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ADC08D15201.1.6 The LVDS Outputs
The Data, Out Of Range (OR+/-), and Data Clock (DCLK+/-)outputs are LVDS. The electrical specifications of the LVDSoutputs are compatible with typical LVDS receivers availableon ASIC and FPGA chips; but they are not IEEE or ANSIcommunications standards compliant due to the low +1.9Vsupply used on this chip. The user is given the choice of alower signal amplitude via the OutV control pin or the OVcontrol register bit. For short LVDS lines and low noise sys-tems, satisfactory performance may be realized with the OutVinput low, which results in lower power consumption. If theLVDS lines are long and/or the system in which the AD-C08D1520 is used is noisy, it may be necessary to tie theOutV pin high.
The LVDS data outputs have a typical common mode voltageof 800 mV when the VBG pin is unconnected and floating. If ahigher common mode is required, this common mode voltagecan be increased to 1175 mV by tying the VBG pin to VA .IMPORTANT NOTE: Tying the VBG pin to VA will also in-crease the differential LVDS output voltage by up to 40mV.1.1.7 Power Down
The ADC08D1520 is in the active state when the Power Downpin (PD) is low. When the PD pin is high, the device is in thepower down mode. In this mode, the data output pins (bothpositive and negative) are put into a high impedance state andthe device's power consumption is reduced to a minimal level.A logic high on the Power Down Q-channel (PDQ) pin willpower down the Q-channel and leave the I-channel active.There is no provision to power down the I-channel indepen-dently of the Q-channel. Upon return to normal operation, thepipeline will contain meaningless information.
If the PD input is brought high while a calibration is running,the device will not go into power down until the calibrationsequence is complete. However, if power is applied and PDis already high, the device will not begin the calibration se-quence until PD is brought low. If a manual calibration isrequested while the device is powered down, the calibrationwill not take place at all. That is, the manual calibration inputis completely ignored in the power down state. Calibration willfunction with the Q-channel powered down, but that channelwill not be calibrated if PDQ is high. If the Q-channel is sub-sequently to be used, it is necessary to perform a calibrationafter PDQ is brought low.
1.2 NON-EXTENDED AND EXTENDED CONTROL MODEThe ADC08D1520 may be operated in one of two controlmodes: Non-extended Control Mode or Extended ControlMode. In the simpler Non-extended Control Mode, the useraffects available configuration and control of the devicethrough several control pins. The Extended Control Modeprovides additional configuration and control options througha serial interface and a set of 9 registers. Extended ControlMode is selected by setting pin 41 to logic low. If pin 41 isfloating and pin 52 is floating or logic high, pin 14 can alter-nately be used to enable the Extended Control Mode. Thechoice of control modes is required to be a fixed selection andis not intended to be switched dynamically while the device isoperational.
Table 3 shows how several of the device features are affectedby the control mode chosen.
TABLE 3. Features and Modes
Feature
SDR or DDR ClockingDDR Clock Phase
SDR Data transitions with rising orfalling DCLK edge
Non-Extended Control ModeSelected with pin 4
Not Selectable (0° Phase Only)SDR Data transitions with rising edge ofDCLK+ when pin 4 is logic high and onfalling edge when low.
Normal differential data and DCLKamplitude selected when pin 3 is logichigh and reduced amplitude selectedwhen low.
Extended Control Mode
Selected with nDE in the ConfigurationRegister (Addr-1h; bit-10).
Selected with DCP in the ConfigurationRegister (Addr-1h; bit-11).
Selected with OED in the ConfigurationRegister (Addr-1h; bit-8).
LVDS output level
Selected with OV in the ConfigurationRegister (Addr-1h; bit-9).
Power-On Calibration Delay
Short delay selected when pin 127 is logic
Short delay only.
low and longer delay selected when high.Normal input full-scale range selectedwhen pin 14 is logic high and reducedrange when low. Selected range appliesto both channels.
Up to 512 step adjustments over anominal range specified in 1.4
REGISTER DESCRIPTION. Separaterange selected for I- and Q-channels.Selected using Full Range Registers(Addr-3h and Bh; bit-7 through 15).512 steps of adjustment using the InputOffset register specified in 1.4
REGISTER DESCRIPTION for eachchannel using Input Offset Registers(Addr-2h and Ah; bit-7 thru 15).
Full-Scale Range
Input Offset AdjustNot possible
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ADC08D1520Dual Edge Sampling SelectionDual Edge Sampling Input ChannelSelection
Enabled by programming DEN in the
Enabled with pin 127 floating or tied to half
Extended Configuration Register
the supply
(Addr-9h; bit-13).Only I-channel Input can be used
Either I- or Q-channel input may besampled by both ADCs.
A test pattern can be made present atthe data outputs by setting TPO to 1b inExtended Configuration Register(Addr-9h; bit-15).
The DCLK outputs will continuously bepresent when RTD is set to 1b inExtended Configuration Register(Addr-9h; bit-14 to 7).
If the device is set in DDR, the output canbe programmed to be non-demultiplexed. When OED inConfiguration Register is set 1b(Addr-1h; bit-8), this selects non-demultiplex. If OED is set 0b, this selects1:2 demultiplex.
The OR outputs can be programmed tobecome a second DCLK output whennSD is set 0b in Configuration Register(Addr-1h; bit-13).
The sampling clock phase can be
manually adjusted through the Coarseand Intermediate Register (Addr-Fh;bit-15 to 7) and Fine Register (Addr-Eh;bit-15 to 8).
Test PatternNot possible
Resistor Trim DisableNot possible
Selectable Output DemultiplexerNot possible
Second DCLK OutputNot possible
Sampling Clock Phase AdjustNot possible
The default state of the Extended Control Mode is set uponpower-on reset (internally performed by the device) and isshown in Table 4.
TABLE 4. Extended Control Mode Operation
(Pin 41 Logic Low or Pin 52 Logic High or Floating and Pin 14 Floating or VA/2)
Feature
SDR or DDR ClockingDDR Clock PhaseLVDS Output Amplitude
Calibration DelayFull-Scale RangeInput Offset AdjustDual Edge Sampling (DES)
Test PatternResistor Trim DisableSelectable Output Demultiplexer
Second DCLK OutputSampling Clock Phase Adjust
Extended Control Mode Default State
DDR Clocking
Data changes with DCLK edge (0° phase)Normal amplitude
(See VOD in Converter Electrical Characteristics)Short Delay
(See tCalDly in Converter Electrical Characteristics)Normal range for both channels
(See VIN in Converter Electrical Characteristics)
No adjustment for either channel
Not enabledNot present at output
Trim enabled, DCLK not continuously present at output
1:2 Demultiplex
Not present, pin 79 and 80 function as OR+ and OR-, respectively
No adjustment for fine, intermediate or coarse
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ADC08D15201.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serialinterface, all nine registers must be written with desired ordefault values. Subsequent writes to single registers are al-lowed.
The 3-pin serial interface is enabled only when the device isin the Extended Control Mode. The pins of this interface areSerial Clock (SCLK), Serial Data (SDATA) and Serial Inter-face Chip Select (SCS). Nine write only registers are acces-sible through this serial interface.
SCS: This signal should be asserted low while accessing aregister through the serial interface. Setup and hold times withrespect to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of thissignal. There is no minimum frequency requirement for SCLK.SDATA: Each register access requires a specific 32-bit pat-tern at this input. This pattern consists of a header, registeraddress and register value. The data is shifted in MSB first.Setup and hold times with respect to the SCLK must be ob-served.
Each Register access consists of 32 bits, as shown in Figure6 of the Timing Diagrams. The fixed header pattern is 00000000 0001 (eleven zeros followed by a 1). The loading se-quence is such that a \"0\" is loaded first. These 12 bits formthe header. The next 4 bits are the address of the register thatis to be written to and the last 16 bits are the data written tothe addressed register. The addresses of the various regis-ters are indicated in Table 5.
Refer to 1.4 REGISTER DESCRIPTION for information onthe data to be written to the registers.
Subsequent register accesses may be performed immediate-ly, starting with the 33rd SCLK. This means that the SCS inputdoes not have to be de-asserted and asserted again betweenregister addresses. It is possible, although not recommended,to keep the SCS input permanently enabled (logic low) whenusing Extended Control Mode.
Control register contents are retained when the device is putinto power-down mode.
IMPORTANT NOTE: Do not write to the Serial Interface whencalibrating the ADC. Doing so will impair the performance ofthe device until it is re-calibrated correctly. Programming theserial registers will also reduce dynamic performance of theADC for the duration of the register access time.
TABLE 5. Register Addresses
4-Bit Address
Loading Sequence:
A3 loaded after Fixed Header pattern, A0 loaded lastA3A2A1000000001111111
000011110000111
001100110011001
A0Hex010101010101010
0h1h2h3h4h5h6h7h8h9hAhBhChDhEh
Register Addressed
CalibrationConfigurationI-channel OffsetI-channel Full-ScaleVoltage Adjust
ReservedReservedReservedReservedReserved
Extended ConfigurationQ-channel OffsetQ-channel Full-ScaleVoltage Adjust
ReservedReservedSampling Clock Phase
Fine AdjustSample Clock PhaseIntermediate and Coarse
Adjust
1111Fh
1.4 REGISTER DESCRIPTION
Nine write-only registers provide several control and config-uration options in the Extended Control Mode. These regis-ters have no effect when the device is in the Non-extendedControl Mode. Each register description below also shows thePower-On Reset (POR) state of each control bit.
Calibration Register
Addr: 0h (0000b)D15CALD71Bit 15
D141D61
D131D51
D121D41
D111D31
Write only (0x7FFF)D101D21
D91D11
D81D01
Bits 14:0
CAL: Calibration Enable. When this bit is set1b, an on-command calibration cycle isinitiated. This function is exactly the same asissuing an on-command calibration using theCAL pin. This bit is OR'd with the CAL pin(30).
POR State: 0bMust be set to 1b
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ADC08D1520Configuration Register
Addr: 1h (0001b)D151D71Bit 15Bit 14Bit 13
D140D61
D13nSDD51
D12
D11
Write only (0xB2FF)D10nDED21
D9OVD11
D8OEDD01
Bit 8
DCSDCPD41
D31
Bit 12
Bit 11
Bit 10
Bit 9
Must be set to 1bMust be set to 0b
nSD: Second DCLK Output. When this bit is1b, the device only has one DCLK output andone OR output. When this output is 0b, thedevice has two identical DCLK outputs and noOR output.POR State: 1b
DCS: Duty Cycle Stabilizer. When this bit is setto 1b, a duty cycle stabilization circuit isapplied to the clock input. When this bit is setto 0b the stabilization circuit is disabled.POR State: 1b
DCP: DDR Clock Phase. This bit only has aneffect in the DDR mode. When this bit is set to0b, the DCLK edges are time-aligned with thedata bus edges (\"0° Phase\"). When this bit isset to 1b, the DCLK edges are placed in themiddle of the data bit-cells (\"90° Phase\"),using the one-half speed DCLK shown inFigure 4 as the phase reference.POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,data bus clocking follows the DDR modewhereby a data word is output with each risingand falling edge of DCLK. When this bit is setto a 1b, data bus clocking follows the SDRmode whereby each data word is output witheither the rising or falling edge of DCLK, asdetermined by the OutEdge bit.POR State: 0b
OV: Output Voltage. This bit determines theLVDS outputs' voltage amplitude and has thesame function as the OutV pin that is used inthe Non-extended Control Mode. When this bitis set to 1b, the normal output amplitude isused. When this bit is set to 0b, the reducedoutput amplitude is used. See VOD inConverter Electrical Characteristics.POR State: 1b
Bits 7:0
OED: Output Edge and Demultiplex Control.This bit has two functions. When the device isin SDR mode, this bit selects the DCLK edgewith which the data words transition and hasthe same effect as the OutEdge pin in the Non-extended Control Mode. When this bit is set to1b, the data outputs change with the risingedge of DCLK+. When this bit is set to 0b, thedata output changes with the falling edge ofDCLK+. When the device is in DDR mode, thisbit selects the Non-demultiplexed Mode whenset to 1b. When the bit set to 0b, the device isprogrammed into the Demultiplexed Mode. Ifthe device is in DDR and Non-DemultiplexedMode, then the DCLK has a 0° phaserelationship with the data; it is not possible toselect the 90° phase relationship.POR State: 0bMust be set to 1b
MPORTANT NOTE: It is recommended that this registershould only be written upon power-up initialization as writingit may cause disturbance on the DCLK output as this signal'sbasic configuration is changed.
I-Channel Offset
Addr: 2h (0010b)D15(MSB)D7SignBits 15:8
D61
D51
D14
D13
D12
D11
Write only (0x007F)D10
D9
D8(LSB)
D21
D11
D01
Offset ValueD41
D31
Bit 7
Bit 6:0
Offset Value. The input offset of the I-channelADC is adjusted linearly and monotonically bythe value in this field. 00h provides a nominalvalue of zero offset, while FFh provides anominal value of 45 mV of offset. Thus, eachcode step provides 0.176 mV of offset.POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b givesnegative offset, resulting in total offsetadjustment of ±45 mV.POR State: 0bMust be set to 1b
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ADC08D1520I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)D15(MSB)D7(LSB)Bit 15:7
D61
D51
D14
D13
D12
Write only (0x807F)D11
D10
D9
D8
Bit 12
IS: Input Select. When this bit is set to 0b theI-channel is operated upon by both ADCs.When this bit is set to 1b the Q-channel isoperated on by both ADCs.POR State: 0bMust be set to 0b
DLF: DES Low Frequency. When this bit isset 1b, the dynamic performance of thedevice is improved when the input clock isless than 900 MHz.POR State: 0bMust be set to 1b
Q-Channel Offset
Adjust ValueD41
D31
D21
D11
D01
Bit 11Bit 10
Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I-channel isadjusted linearly and monotonically with a 9 bitdata value. The adjustment range is ±20% ofthe nominal 700 mVP-P differential value.0000 0000 01000 0000 0Default Value1111 1111 1
560mVP-P700mVP-P840mVP-P
Bits 9:0
Addr: Ah (1010b)D15(MSB)D7SignBit 15:8
D61
D51
D14
D13
D12
D11
Write only (0x007F)D10
D9
D8(LSB)
D21
D11
D01
Offset ValueD41
D31
Bits 6:0
For best performance, it is recommended thatthe value in this field be limited to the range of0110 0000 0b to 1110 0000 0b, i.e., limit theamount of adjustment to ±15%. The remaining±5% headroom allows for the ADC's own fullscale variation. A gain adjustment does notrequire ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)Must be set to 1b
Extended Configuration Register
Addr: 9h (1001b)D15TPOD71Bit 15
D14RTDD61
D13DEND51
D12ISD41
D110D31
Write only (0x03FF)D10DLFD21
D91D11
D81D01
Bit 7
Bit 6:0
Offset Value. The input offset of the Q-channelADC is adjusted linearly and monotonically bythe value in this field. 00h provides a nominalzero offset, while FFh provides a nominal 45mV of offset. Thus, each code step providesabout 0.176 mV of offset.POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b givesnegative offset.POR State: 0bMust be set to 1b
Q-Channel Full-Scale Voltage Adjust
Addr: Bh (1011b)D15(MSB)D7(LSB)Bit 15:7
D61
D51
D14
D13
D12
Write only (0x807F)D11
D10
D9
D8
TPO: Test Pattern Output. When this bit is set1b, the ADC is disengaged and a test patterngenerator is connected to the outputs
including OR. This test pattern will work withthe device in the SDR, DDR and the Non-demux Modes (DES and Non-DES).POR State: 0b
RTD: Resistor Trim Disable. When this bit isset to 1b, the input termination resistor is nottrimmed during the calibration cycle and theDCLK output remains enabled. Note that theADC is calibrated regardless of this setting.POR State: 0b
DEN: DES Enable. Setting this bit to 1benables the Dual Edge Sampling Mode. Inthis mode, the ADCs in this device are usedto sample and convert the same analog inputin a time-interleaved manner, accomplishinga sample rate of twice the input clock rate.When this bit is set to 0b, the device operatesin the Non-DES Modes.POR State: 0b
Adjust ValueD41
D31
D21
D11
D01
Bit 14
Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the Q-channel ADC isadjusted linearly and monotonically with a 9 bitdata value. The adjustment range is ±20% ofthe nominal 700 mVP-P differential value.0000 0000 01000 0000 01111 1111 1
560 mVP-P700 mVP-P840 mVP-P
Bit 13
Bits 6:0
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For best performance, it is recommended thatthe value in this field be limited to the range of0110 0000 0b to 1110 0000 0b, i.e., limit theamount of adjustment to ±15%. The remaining±5% headroom allows for the ADC's own fullscale variation. A gain adjustment does notrequire ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)Must be set to 1b
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ADC08D1520Sample Clock Phase Fine Adjust
Addr: Eh (1110b)D15(MSB)D71Bits 15:8
D61D14
D13
D12
D11
Write only (0x00FF)D10
D9
D8(LSB)D11
D01
Fine Phase AdjustD51
D41
D31
D21
grammed when necessary. For example, if a user wishes toenable the test pattern, only the Test Pattern register shouldbe programmed. A user should avoid developing softwareroutines which program all the registers when the data con-tents of only one register is being modified.
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1520 has the capability to precisely reset itssampling clock input to DCLK output relationship as deter-mined by the user-supplied DCLK_RST pulse. This allowsmultiple ADCs in a system to have their DCLK (and data) out-puts transition at the same time with respect to the sharedCLK input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-ments that are shown in Figure 7, Figure 8 and Figure 9 of theTiming Diagrams. The DCLK_RST pulse must be of a mini-mum width and its deassertion edge must observe setup andhold times with respect to the CLK input rising edge. Thesetiming specifications are listed as tPWR, tRS and tRH in theConverter Electrical Characteristics.
The DCLK_RST signal can be asserted asynchronously tothe input clock. If DCLK_RST is asserted, the DCLK output isheld in a designated state. The state in which DCLK is heldduring the reset period is determined by the mode of operation(SDR or DDR) and the setting of the Output Edge configura-tion pin or bit. (Refer to Figure 7, Figure 8 and Figure 9 for theDCLK reset state conditions). Therefore, depending uponwhen the DCLK_RST signal is asserted, there may be a nar-row pulse on the DCLK line during this reset event. When theDCLK_RST signal is de-asserted in synchronization with theCLK rising edge, there are three or four CLK cycles of sys-tematic delay and the next CLK falling edge synchronizes theDCLK output with those of other ADC08D1520s in the sys-tem. The DCLK output is enabled again after a constant delay(relative to the input clock frequency) which is equal to theCLK input to DCLK output delay (tOD). The device always ex-hibits this delay characteristic in normal operation. The userhas the option of using a single-ended DCLK_RST signal, buta differential DCLK_RST is strongly recommended due to itssuperior timing specifications.
As shown in Figure 7, Figure 8, and Figure 9 of the TimingDiagrams, there is a delay from the deassertion ofDCLK_RST to the reappearance of DCLK, which is equal toseveral CLK cycles of delay plus tOD. Note that the deasser-tion of DCLK_RST is not latched in until the next falling edgeof CLK. For 1:2 Demux 0° Mode, there are four CLK cycles ofdelay; for all other modes, there are three CLK cycles of delay.If the device is not programmed to allow DCLK to run contin-uously, DCLK will become inactive during a calibration cycle.Therefore, it is strongly recommended that DCLK only beused as a data capture clock and not as a system clock.The DCLK_RST pin should NOT be brought high while thecalibration process is running (while CalRun is high). Doingso could cause a glitch in the digital circuitry, resulting in cor-ruption and invalidation of the calibration.
1.6 ADC TEST PATTERN
To aid in system debug, the ADC08D1520 has the capabilityof providing a test pattern at the four output ports completelyindependent of the input signal. The ADC is disengaged anda test pattern generator is connected to the outputs, includingOR+/-. The test pattern output is the same in DES Mode andNon-DES Mode. Each port is given a unique 8-bit word, al-ternating between 1's and 0's as described in the Table 6 andTable 7.
Fine Phase Adjust. The phase of the ADCsampling clock is adjusted linearly and
monotonically by the value in this field. 00hprovides a nominal zero phase adjustment,while FFh provides a nominal 50 ps of delay.Thus, each code step provides about 0.2 psof delay.
POR State: 0000 0000bMust be set to 1b
Bits 7:0
Sample Clock Phase Intermediate/Coarse AdjustAddr: Fh (1111b)D15POLD7(LSB)Bit 15
D14
D13
D12
Write only (0x007F)D11
D10
D9IPAD11
D01D8
(MSB) Coarse Phase AdjustD61
D51
D41
D31
D21
Polarity Select. When this bit is selected, thepolarity of the ADC sampling clock isinverted.
POR State: 0b
Bits 14:10Coarse Phase Adjust. Each code value in
this field delays the sample clock by
approximately 65 ps. A value of 00000b inthis field causes zero adjustment.POR State: 00000bBits 9:7
Intermediate Phase Adjust. Each code valuein this field delays the sample clock by
approximately 11 ps. A value of 000b in thisfield causes zero adjustment. Maximumcombined adjustment using Coarse PhaseAdjust and Intermediate Phase adjust isapproximately 2.1ns.POR State: 000bMust be set to 1b
Bits 6:0
1.4.1 Clock Phase Adjust
This is a feature intended to help the system designer removesmall imbalances in clock distribution traces at the board levelwhen multiple ADCs are used. However, enabling this featurewill reduce the dynamic performance (ENOB, SNR, SFDR)some finite amount. The amount of degradation increaseswith the amount of adjustment applied. The user is stronglyadvised to (a) use the minimal amount of adjustment; and (b)verify the net benefit of this feature in his system before relyingon it.
1.4.2 DCLK Output During Register Programming
When programming the Configuration register, the DCLK out-put may be disrupted and is invalid. The DCLK output is notvalid until the register data has not been completely shiftedand latched into the register and the register is in a knownprogrammed state. To minimize disrupting the DCLK output,it is recommend that the Configuration Register only be pro-www.national.com
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ADC08D1520TABLE 6. Test Pattern by Output Port
in 1:2 Demultiplex Mode
TimeT0T1T2T3T4T5T6T7T8T9T10T11
Qd01hFEh01hFEh01h01hFEh01hFEh01h01h...
Id02hFDh02hFDh02h02hFDh02hFDh02h02h...
Q03hFCh03hFCh03h03hFCh03hFCh03h03h...
I04hFBh04hFBh04h04hFBh04hFBh04h04h...
OR01010010100...
PatternSequence n+2PatternSequencen+1PatternSequence
nComments
The internal bandgap-derived reference voltage has a nomi-nal value of VIN , as determined by the FSR pin and describedin1.1.4 The Analog Inputs.
There is no provision for the use of an external reference volt-age, but the full-scale input voltage can be adjusted througha Configuration Register in the Extended Control Mode, asexplained in 1.2 NON-EXTENDED AND EXTENDED CON-TROL MODE.
Differential input signals up to the chosen full-scale level willbe digitized to 8 bits. Signal excursions beyond the full-scalerange will be clipped at the output. These large signal excur-sions will also activate the OR output for the time that thesignal is out of range. See 2.2.3 Out Of Range Indication.One extra feature of the VBG pin is that it can be used to raisethe common mode voltage level of the LVDS outputs. Theoutput offset voltage (VOS) is typically 800 mV when the VBGpin is used as an output or left floating. To raise the LVDSoffset voltage to the typical value, the VBG pin can be con-nected directly to the supply rail.
2.2 THE ANALOG INPUT
The analog input is differential and the signal source may bea.c. or d.c. coupled. In the Non-extended Control Mode, thefull-scale input range is selected using the FSR pin as spec-ified in the Converter Electrical Characteristics. In the Ex-tended Control Mode, the full-scale input range is selected byprogramming the Full-Scale Voltage Adjust register throughthe Serial Interface. For best performance when adjusting theinput full-scale range in the Extended Control Mode, refer to1.4 REGISTER DESCRIPTION for guidelines on limiting theamount of adjustment.
Table 8 gives the input to output relationship with the FSR pinhigh when the Non-extended Control Mode is used. With theFSR pin grounded, the millivolt values in Table 8 are reducedto 75% of the values indicated. In the Extended Control Mode,these values will be determined by the full scale range andoffset settings in the Control Registers.
TABLE 8. Differential Input To Output Relationship
(Non-Extended Control Mode, FSR High)
With the part programmed into the Non-demultiplex Mode, thetest pattern’s order will be as described in Table 7.
TABLE 7. Test Pattern by Output Port in
Non-demultiplex ModeTimeT0T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15
Q01hFEh01h01hFEhFEh01h01hFEh01h01hFEh01h01hFEh...
I02hFDh02h02hFDhFDh02h02hFDh02h02hFDh02h02hFDh...
OR010011001001001...
PatternSequencen+1PatternSequence
nComments
VIN+VCM − 217.5 mVVCM − 109 mV
VCM
VCM + 109 mVVCM + 217.5 mV
VIN−VCM + 217.5 mVVCM + 109 mV
VCMVCM −109 mVVCM − 217.5 mV
Output Code0000 00000100 00000111 1111 /1000 00001100 00001111 1111
Depending upon how it is initiated, the I- and the Q- channels'test patterns may or may not be synchronized. Either I and Idor Q and Qd patterns may be behind by one DCLK.
To ensure that the test pattern starts synchronously in eachport, set DCLK_RST while writing the Test Pattern Output bitin the Extended Configuration Register. The pattern appearsat the data output ports when DCLK_RST is cleared low. Thetest pattern will work at speed and with the device in the SDR,DDR and the Non-demux Modes (DES and Non-DES).
2.0 Applications Information
2.1 THE REFERENCE VOLTAGE
The reference voltage for the ADC08D1520 is derived from a1.2V bandgap reference, a buffered version of which, ismade available at VBG (pin 31) for the user.
This output has an output current capability of ±100 μA andshould be buffered if more current than this is required.
The buffered analog inputs simplify the task of driving theseinputs so that the RC pole which is generally used at samplingADC inputs is not required. If the user desires to place anamplifier circuit before the ADC, care should be taken inchoosing an amplifier with adequate noise and distortion per-formance, and adequate gain at the frequencies used for theapplication.
Note that a precise d.c. common mode voltage must bepresent at the ADC inputs. This common mode voltage,VCMO, is provided on-chip when a.c. input coupling is usedand the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the VCMO output must begrounded, as shown in Figure 11. This causes the on-chipVCMO voltage to be connected to the inputs through on-chip50 kΩ resistors.
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ADC08D1520IMPORTANT NOTE: An analog input channel that is not used(e.g. in DES Mode) should be connected to a.c. ground (i.e.,capacitors to ground) when the inputs are a.c. coupled. Donot connect an unused analog input directly to ground.
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FIGURE 11. VCMO Drive for A.C. Coupled Differential InputWhen the d.c. coupled mode is used, a common mode volt-age must be provided at the differential inputs. This commonmode voltage should track the VCMO output pin. Note that theVCMO output potential will change with temperature. The com-mon mode output of the driving device should track thischange.
IMPORTANT NOTE: An analog input channel that is not used(e.g. in DES Mode) should be tied to the VCMO voltage whenthe inputs are d.c. coupled. Do not connect unused analoginputs to ground.
Full-scale distortion performance falls off rapidly as theinput common mode voltage deviates from VCMO. This isa direct result of using a very low supply voltage to min-imize power. Keep the input common voltage within 50mV of VCMO.
Performance is as good in the d.c. coupled mode as it is inthe a.c. coupled mode, provided the input common modevoltage at both analog inputs remains within 50 mV of VCMO.2.2.1 Single-Ended Input Signals
There is no provision for the ADC08D1520 to adequately pro-cess single-ended input signals. The best way to handlesingle-ended signals is to convert them to differential signalsbefore presenting them to the ADC. The easiest way to ac-complish single-ended to differential signal conversion is withan appropriate balun-connected transformer, as shown inFigure 12.
Figure 12 is a generic depiction of a single-ended to differen-tial signal conversion using a balun. The circuitry specific tothe balun will depend upon the type of balun selected and theoverall board layout. It is recommended that the system de-signer contact the manufacturer of the balun in order to aid indesigning the best performing single-ended to differentialconversion circuit.
When selecting a balun, it is important to understand the inputarchitecture of the ADC. There are specific balun parameters,of which the system designer should be mindful. Theimpedance of the analog source should be matched to theADC08D1520's on-chip 100Ω differential input terminationresistor. The range of this termination resistor is described inthe Converter Electrical Characteristics as the specificationRIN.
Also, the phase and amplitude balance are important. Thelowest possible phase and amplitude imbalance is desiredwhen selecting a balun. The phase imbalance should be nomore than ±2.5° and the amplitude imbalance should be lim-ited to less than 1dB at the desired input frequency range.Finally, when selecting a balun, the VSWR (Voltage StandingWave Ratio), bandwidth and insertion loss of the balun shouldalso be considered. The VSWR aids in determining the overalltransmission line termination capability of the balun when in-terfacing to the ADC input. The insertion loss should beconsidered so that the signal at the balun output is within thespecified input range of the ADC; see VIN in the ConverterElectrical Characteristics.
2.2.2. D.C. Coupled Input Signals
When d.c. coupling to the ADC08D1520 analog inputs, sin-gle-ended to differential conversion may be easily accom-plished with the LMH6555, as shown in Figure 13. In suchapplications, the LMH6555 performs the task of single-endedto differential conversion while delivering low distortion andnoise, as well as output balance, that supports the operationof the ADC08D1520. Connecting the ADC08D1520 VCMO pinto the VCM_REF pin of the LMH6555, via an appropriate buffer,will ensure that the common mode input voltage meets therequirements for optimum performance of the ADC08D1520.The LMV321 was chosen to buffer VCMD for its low voltageoperation and reasonable offset voltage.
The output current from the ADC08D1520 VCMO pin shouldbe limited to 100 μA.
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FIGURE 12. Single-Ended to Differential Signal
Conversion Using a Balun
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FIGURE 13. Example of Using LM6555 for D.C. Coupled Input
In Figure 13, RADJ- and RADJ+ are used to adjust the differentialoffset that can be measured at the ADC inputs VIN+ and VIN-with the LMH6555's input terminated to ground as shown, butnot driven and with no RADJ resistors present. An unadjustedpositive offset with reference to VIN- greater than |15mV|should be reduced with a resistor in the RADJ- position. Like-wise, an unadjusted negative offset with reference to VIN-greater than |15mV| should be reduced with a resistor in theRADJ+ position. Table 9 gives suggested RADJ- and RADJ+ val-ues for various unadjusted differential offsets to bring the VIN+ and VIN- offset back to within |15mV|.
TABLE 9. Resistor Values for Offset AdjustmentUnadjusted Offset Reading
0mV to 10mV11mV to 30mV31mV to 50mV51mV to 70mV71mV to 90mV91mV to 110mV
Resistor Valueno resistor needed
20.0kΩ10.0kΩ6.81kΩ4.75kΩ3.92kΩ
DR are obtained with the FSR pin low. The LMH6555 ofFigure 13 is suitable for any Full Scale Range.
2.3 THE CLOCK INPUTS
The ADC08D1520 has differential LVDS clock inputs, CLK+and CLK-, which must be driven with an a.c. coupled, differ-ential clock signal. Although the ADC08D1520 is tested andits performance is guaranteed with a differential 1.5 GHzclock, it will typically function well with input clock frequencyrange; see fCLK(min) and fCLK(max) in the Converter ElectricalCharacteristics. The clock inputs are internally terminatedand biased. The input clock signal must be capacitively cou-pled to the clock pins as indicated in Figure 14.
Operation up to the sample rates indicated in the ConverterElectrical Characteristics is typically possible if the maximumambient temperatures indicated are not exceeded. Operatingat higher sample rates than indicated for the given ambienttemperature may result in reduced device reliability and prod-uct lifetime. This is because of the higher power consumptionand die temperatures at high sample rates. Important also forreliability is proper thermal management. See 2.6.2 ThermalManagement.
2.2.3 Out Of Range Indication
When the conversion result is clipped, the Out of Range (OR)output is activated such that OR+ goes high and OR- goeslow. This output is active as long as accurate data on eitheror both of the buses would be outside the range of 00h to FFh.When the device is programmed to provide a second DCLKoutput, the OR signals become DCLK2. Refer to 1.4 REGIS-TER DESCRIPTION.
2.2.4 Full-Scale Input Range
As with all A/D Converters, the input range is determined bythe value of the ADC's reference voltage. The reference volt-age of the ADC08D1520 is derived from an internal band-gapreference. The FSR pin controls the effective reference volt-age of the ADC08D1520 such that the differential full-scaleinput range at the analog inputs is a normal amplitude withthe FSR pin high, or a reduced amplitude with FSR pin low;see VIN in the Converter Electrical Characteristics. The bestSNR is obtained with FSR high, but better distortion and SF-
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FIGURE 14. Differential (LVDS) Input Clock ConnectionThe differential input clock line pair should have a character-istic impedance of 100Ω and (when using a balun), be termi-nated at the clock source in that (100Ω) characteristicimpedance. The input clock line should be as short and asdirect as possible. The ADC08D1520 clock input is internallyterminated with an untrimmed 100Ω resistor.
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ADC08D1520Insufficient input clock levels will result in poor dynamic per-formance. Excessively high input clock levels could cause achange in the analog input offset voltage. To avoid this, keepthe input clock level (VID) within the range specified in theConverter Electrical Characteristics.
The low and high times of the input clock signal can affect theperformance of any A/D Converter. The ADC08D1520 fea-tures a duty cycle clock correction circuit which can maintainperformance over the 20%-to-80% specified duty cyclerange, even in DES Mode. The ADC will meet its performancespecification if the input clock high and low times are main-tained within the duty cycle range; see the Converter Electri-cal Characteristics.
High speed, high performance ADCs such as the AD-C08D1520 require a very stable input clock signal with mini-mum phase noise or jitter. ADC jitter requirements are definedby the ADC resolution (number of bits), maximum ADC inputfrequency and the input signal amplitude relative to the ADCinput full scale range. The maximum jitter (the sum of the jitterfrom all sources) allowed to prevent a jitter-induced reductionin SNR is found to be
tJ(MAX) = ( VINFSR/ VIN(P-P)) x (1/(2(N+1) x π x fIN))where tJ(MAX) is the rms total of all jitter sources in seconds,VIN(P-P) is the peak-to-peak analog input signal, VINFSR is thefull-scale range of the ADC, \"N\" is the ADC resolution in bitsand fIN is the maximum input frequency, in Hertz, at the ADCanalog input.
Note that the maximum jitter described above is the RSS sumof the jitter from all sources, including that in the ADC inputclock, that added by the system to the ADC input clock andinput signals and that added by the ADC itself. Since the ef-fective jitter added by the ADC is beyond user control, the bestthe user can do is to keep the sum of the externally addedinput clock jitter and the jitter added by the analog circuitry tothe analog signal to a minimum.
Input clock amplitudes above those specified in the ConverterElectrical Characteristics may result in increased input offsetvoltage. This would cause the converter to produce an outputcode other than the expected 127/128 when both input pinsare at the same potential.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) providea wide range of possibilities in the operation of theADC08D1520 and facilitate its use. These control pins pro-vide Full-Scale Input Range setting, Calibration, CalibrationDelay, Output Edge Synchronization choice, LVDS OutputLevel choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR con-trol input (pin 14) in the Non-extended Control Mode of oper-ation. The input full-scale range is specified as VIN in theConverter Electrical Characteristics. In the Extended ControlMode, the input full-scale range may be programmed usingthe Full-Scale Adjust Voltage register. See 2.2 THE ANALOGINPUT for more information.
2.4.2 Calibration
The ADC08D1520 calibration must be run to achieve speci-fied performance. The calibration procedure is run automati-cally upon power-up and can be run any time on-commandvia the CAL pin (30) or the Calibration register (Addr: 0h, Bit15). The calibration procedure is exactly the same whetherthere is an input clock present upon power up or if the clock
begins some time after application of power. The CalRun out-put indicator is high while a calibration is in progress. Notethat the DCLK outputs are not active during a calibration cycleby default, therefore it is not recommended to use these sig-nals as a system clock unless the Resistor Trim Disablefeature is used (Reg. 9h). The DCLK outputs are continuouslypresent at the output only when the Resistor Trim Disable isactive.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following theapplication of power. This time delay is determined by thesetting of CalDly.
The calibration process will be not be performed if the CALpin is high at power up. In this case, the calibration cycle willnot begin until the on-command calibration conditions aremet. The ADC08D1520 will function with the CAL pin heldhigh at power up, but no calibration will be done and perfor-mance will be impaired. A manual calibration, however, maybe performed after powering up with the CAL pin high. See2.4.2.2 On-Command Calibration.
The internal power-on calibration circuitry comes up in an un-known logic state. If the input clock is not running at power upand the power on calibration circuitry is active, it will hold theanalog circuitry in power down and the power consumptionwill typically be less than 200 mW. The power consumptionwill be normal after the clock starts.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, either bring the CALpin high for a minimum of tCAL_H input clock cycles after it hasbeen low for a minimum of tCAL_L input clock cycles or performthe same operation via the CAL bit in the Calibration register.Holding the CAL pin high upon power up will prevent execu-tion of power-on calibration until the CAL pin is low for aminimum of tCAL_L input clock cycles, then brought high for aminimum of another tCAL_H input clock cycles. The calibrationcycle will begin tCAL_H input clock cycles after the CAL pin isthus brought high. The CalRun signal should be monitored todetermine when the calibration cycle has completed.
The minimum tCAL_L and tCAL_H input clock cycle sequencesare required to ensure that random noise does not cause acalibration to begin when it is not desired. For best perfor-mance, a calibration should be performed 20 seconds or moreafter power up and repeated when the operating temperaturechanges significantly, relative to the specific system designperformance requirements.
By default, on-command calibration also includes calibratingthe input termination resistance and the ADC. However, sincethe input termination resistance, once trimmed at power-up,changes marginally with temperature, the user has the optionto disable the input termination resistor trim, which will guar-antee that the DCLK is continuously present at the outputduring subsequent calibration. The Resistor Trim Disable(RTD) can be programmed in register 9h when in the Extend-ed Control Mode. Refer to 1.4 REGISTER DESCRIPTION forregister programming information.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delaytimes after the application of power to the start of calibration,as described in 1.1.1 Calibration. The calibration delay valuesallow the power supply to come up and stabilize before cali-bration takes place. With no delay or insufficient delay, cali-bration would begin before the power supply is stabilized atits operating value and result in non-optimal calibration coef-
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ADC08D1520ficients. If the PD pin is high upon power-up, the calibrationdelay counter will be disabled until the PD pin is brought low.Therefore, holding the PD pin high during power up will furtherdelay the start of the power-up calibration cycle. The bestsetting of the CalDly pin depends upon the power-on settlingtime of the power supply.
Note that the calibration delay selection is not possible in theExtended Control Mode and the short delay time is used.2.4.3 Output Edge Synchronization
DCLK signals are available to latch the converter output datainto external circuitry. The output data can be synchronizedwith either edge of these DCLK signals. That is, the outputdata transition can be set to occur with either the rising edgeor the falling edge of the DCLK signal, so that either edge ofthat DCLK signal can be used to latch the output data into thereceiving circuit.
When OutEdge (pin 4) is high, the output data is synchronizedwith the rising edge of the DCLK+ (pin 82). When OutEdge islow, the output data is synchronized with the falling edge ofDCLK+.
At the very high speeds, of which the ADC08D1520 is capa-ble, slight differences in the lengths of the DCLK and datalines can mean the difference between successful and erro-neous data capture. The OutEdge pin may be used to capturedata on the DCLK edge that best suits the application circuitand layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV (pin3). The strength of the output drivers is greater with OutV logichigh. With OutV logic low, there is less power consumption inthe output drivers, but the lower output level means de-creased noise immunity.
For short LVDS lines and low noise systems, satisfactory per-formance may be realized with the OutV input low. If the LVDSlines are long and/or the system in which the ADC08D1520is used is noisy, it may be necessary to tie the OutV pin high.2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the twoinput pairs to be routed to both ADCs. The other input pair isdeactivated. One of the ADCs samples the input signal on therising input clock edge (duty cycle corrected); the other ADCsamples the input signal on the falling input clock edge (dutycycle corrected). If the device is in the 1:4 Demux DES Mode,the result is an output data rate 1/4 that of the interleavedsample rate, which is twice the input clock frequency. Data ispresented in parallel on all four output buses in the followingorder: DQd, DId, DQ, DI. If the device is the Non-demux DESMode, the result is an output data rate 1/2 that of the inter-leaved sample rate. Data is presented in parallel on twooutput buses in the following order: DQ, DI.
To use this feature in the Non-extended Control Mode, allowpin 127 to float and the signal at the I-channel input will besampled by both converters. The Calibration Delay will thenonly be a short delay.
In the Extended Control Mode, either input may be used fordual edge sampling. See 1.1.5.1 Dual-Edge Sampling.2.4.6 Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D1520to be entirely powered down (PD) or the Q-channel to bepowered down and the I-channel to remain active (PDQ). See1.1.7 Power Down for details on the power down feature.
The digital data output pins are put into a high impedancestate when the PD pin for the respective channel is high. Uponreturn to normal operation, the pipeline will contain meaning-less information and must be flushed.
If the PD input is brought high while a calibration is running,the device will not go into power down until the calibrationsequence is complete. However, if power is applied and PDis already high, the device will not begin the calibration se-quence until the PD input goes low. If a manual calibration isrequested while the device is powered down, the calibrationwill not begin at all. That is, the manual calibration input iscompletely ignored in the power down state.
2.5 THE DIGITAL OUTPUTS
The ADC08D1520 normally demultiplexes the output data ofeach of the two ADCs on the die onto two LVDS output buses(total of four buses, two for each ADC). For each of the twoconverters, the results of successive conversions started onthe odd falling edges of the CLK+ pin are available on one ofthe two LVDS buses, while the results of conversions startedon the even falling edges of the CLK+ pin are available on theother LVDS bus. This means that, the word rate at each LVDSbus is 1/2 the ADC08D1520 input clock rate and the two bus-es must be multiplexed to obtain the entire 1.5 GSPS con-version result.
Since the minimum recommended input clock rate for thisdevice is 200 MSPS (in 1:2 Demux Non-DES Mode), the ef-fective rate can be reduced to as low as 100 MSPS by usingthe results available on just one of the two LVDS buses anda 200 MHz input clock, decimating the 200 MSPS data by two.There is one LVDS output clock pair (DCLK+/-) available foruse to latch the LVDS outputs on all buses. There is also asecond LVDS output clock pair (DCLK2+/-) which is optionallyavailable for the same purpose. Whether the data is sent atthe rising or falling edge of DCLK is determined by the senseof the OutEdge pin, as described in 2.4.3 Output Edge Syn-chronization.
Double Data Rate (DDR) clocking can also be used. In thismode, a word of data is presented with each edge of DCLK,reducing the DCLK frequency to 1/4 the input clock frequency.See the Timing Diagrams for details.
The OutV pin is used to set the LVDS differential output levels.See 2.4.4 LVDS Output Level Control.
The output format is Offset Binary. Accordingly, a full-scaleinput level with VIN+ positive with respect to VIN− will producean output code of all ones; a full-scale input level with VIN−positive with respect to VIN+ will produce an output code of allzeros; when VIN+ and VIN− are equal, the output code will varybetween codes 127 and 128. A non-demultiplexed mode ofoperation is available for those cases where the digital ASICis capable of higher speed operation.
2.6 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupttheir own power supplies if not adequately bypassed. A 33 µFcapacitor should be placed within an inch (2.5 cm) of the A/Dconverter power pins. A 0.1 µF capacitor should be placed asclose as possible to each VA pin, preferably within one-halfcentimeter. Leadless chip capacitors are preferred becausethey have low lead inductance.
The VA and VDR supply pins should be isolated from eachother to prevent any digital noise from being coupled into theanalog portions of the ADC. A ferrite choke, such as the JWMiller FB20009-3B, is recommended between these supplylines when a common source is used for them.
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ADC08D1520As is the case with all high speed converters, theADC08D1520 should be assumed to have little power supplynoise rejection. Any power supply used for digital circuitry ina system where a lot of digital power is being consumedshould not be used to supply power to the ADC08D1520. TheADC supplies should be the same supply used for other ana-log circuitry, if not a dedicated supply.
2.6.1 Supply Voltage
The ADC08D1520 is specified to operate with a supply volt-age of 1.9V ±0.1V. It is very important to note that, while thisdevice will function with slightly higher supply voltages, thesehigher supply voltages may reduce product lifetime.
No pin should ever have a voltage on it that is in excess of thesupply voltage or below ground by more than 150 mV, noteven on a transient basis. This can be a problem upon appli-cation of power and power shut-down. Be sure that the sup-plies to circuits driving any of the input pins, analog or digital,do not come up any faster than does the voltage at theADC08D1520 power pins.
The Absolute Maximum Ratings should be strictly observed,even during power up and power down. A power supply thatproduces a voltage spike at turn-on and/or turn-off of powercan destroy the ADC08D1520. The circuit of Figure 15 willprovide supply overshoot protection.
Many linear regulators will produce output spiking at power-on unless there is a minimum load provided. Active devicesdraw very little current until their supply voltages reach a fewhundred millivolts. The result can be a turn-on spike that candestroy the ADC08D1520, unless a minimum load is providedfor the supply. The 100Ω resistor at the regulator output pro-vides a minimum output current during power-up to ensurethere is no turn-on spiking.
In the circuit of Figure 15, an LM317 linear regulator is satis-factory if its input supply voltage is 4V to 5V. If a 3.3V supplyis used, an LM1086 linear regulator is recommended.
power consumption is still high enough to require attention tothermal management. For reliability reasons, the die temper-ature should be kept to a maximum of 130°C. That is, AmbientTemperature (TA) plus ADC power consumption times Junc-tion to Ambient Thermal Resistance (θJA) should not exceed130°C. This is not a problem if TA is kept to a maximum of+85°C as specified in the Operating Ratings section.
The following are general recommendations for mounting ex-posed pad devices onto a PCB. They should be consideredthe starting point in PCB and assembly process development.It is recommended that the process be developed based uponpast experience in package mounting.
The package of the ADC08D1520 has an exposed pad on itsback that provides the primary heat removal path as well asexcellent electrical grounding to the printed circuit board. Theland pattern design for pin attachment to the PCB should bethe same as for a conventional LQFP, but the exposed padmust be attached to the board to remove the maximumamount of heat from the package, as well as to ensure bestproduct parametric performance.
To maximize the removal of heat from the package, a thermalland pattern must be incorporated on the PC board within thefootprint of the package. The exposed pad of the device mustbe soldered down to ensure adequate heat conduction out ofthe package. The land pattern for this exposed pad should beat least as large as the 5 x 5 mm of the exposed pad of thepackage and be located such that the exposed pad of thedevice is entirely over that thermal land pattern. This thermalland pattern should be electrically connected to ground. Aclearance of at least 0.5 mm should separate this land patternfrom the mounting pads for the package pins.
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FIGURE 15. Non-Spiking Power Supply
The output drivers should have a supply voltage, VDR, that iswithin the range specified in the Operating Ratings table. Thisvoltage should not exceed the VA supply voltage.
If the power is applied to the device without an input clocksignal present, the current drawn by the device might be be-low 200 mA. This is because the ADC08D1520 gets resetthrough clocked logic and its initial state is unknown. If thereset logic comes up in the \"on\" state, it will cause most of theanalog circuitry to be powered down, resulting in less than100 mA of current draw. This current is greater than the powerdown current because not all of the ADC is powered down.The device current will be normal after the input clock is es-tablished.
2.6.2 Thermal Management
The ADC08D1520 is capable of impressive speeds and per-formance at very low power levels for its speed. However, the
FIGURE 16. Recommended Package Land PatternSince a large aperture opening may result in poor release, theaperture opening should be subdivided into an array of small-er openings, similar to the land pattern of Figure 16.
To minimize junction temperature, it is recommended that asimple heat sink be built into the PCB. This is done by includ-ing a copper area of about 2 square inches (6.5 square cm)on the opposite side of the PCB. This copper area may beplated or solder coated to prevent corrosion, but should nothave a conformal coating, which could provide some thermalinsulation. Thermal vias should be used to connect these topand bottom copper areas. These thermal vias act as \"heatpipes\" to carry the thermal energy from the device side of theboard to the opposite side of the board where it can be moreeffectively dissipated. The use of 9 to 16 thermal vias is rec-ommended.
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ADC08D1520The thermal vias should be placed on a 1.2 mm grid spacingand have a diameter of 0.30 to 0.33 mm. These vias shouldbe barrel plated to avoid solder wicking into the vias duringthe soldering process as this wicking could cause voids in thesolder between the package exposed pad and the thermalland on the PCB. Such voids could increase the thermal re-sistance between the device and the thermal land on theboard, which would cause the device to run hotter.
If it is desired to monitor die temperature, a temperature sen-sor may be mounted on the heat sink area of the board nearthe thermal vias. Allow for a thermal gradient between thetemperature sensor and the ADC08D1520 die of θJ-PAD timestypical power consumption = 2.8°C/W x 1.8W = 5°C. Allowingfor 6°C, including some margin for temperature drop from thepad to the temperature sensor, would mean that maintaininga maximum pad temperature reading of 124°C will ensure thatthe die temperature does not exceed 130°C. This calculationassumes that the exposed pad of the ADC08D1520 is prop-erly soldered down and the thermal vias are adequate. (Theinaccuracy of the temperature sensor is in addition to theabove calculation).
2.7 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-tial to ensure accurate conversion. A single ground planeshould be used, instead of splitting the ground plane into ana-log and digital areas.
Since digital switching transients are composed largely ofhigh frequency components, the skin effect implies that thetotal ground plane copper weight will have little effect uponthe logic-generated noise. Total surface area is more impor-tant than is total ground plane volume. Coupling between thetypically noisy digital circuitry and the sensitive analog circuit-ry can lead to poor performance that may seem impossible toisolate and remedy. The solution is to keep the analog cir-cuitry well separated from the digital circuitry.
High power digital components should not be located on ornear any linear component or power supply trace or plane thatservices analog or mixed signal components, as the resultingcommon return current path could cause fluctuation in theanalog input “ground” return of the ADC, causing excessivenoise in the conversion result.
Generally, it is assumed that analog and digital lines shouldcross each other at 90° to avoid getting digital noise into theanalog path. In high frequency systems, however, avoidcrossing analog and digital lines altogether. The input clocklines should be isolated from ALL other lines, analog ANDdigital. The generally accepted 90° crossing should be avoid-ed, as even a little coupling can cause problems at highfrequencies. Best performance at high frequencies is ob-tained with a straight signal path.
The analog input should be isolated from noisy signal tracesto avoid coupling of spurious signals into the input. This isespecially important with the low level drive required of theADC08D1520. Any external component (e.g., a filter capaci-tor) connected between the converter's input and groundshould be connected to a very clean point in the analogground plane. All analog circuitry (input amplifiers, filters, etc.)should be separated from any digital components.
2.8 DYNAMIC PERFORMANCE
The ADC08D1520 is a.c. tested and its dynamic performanceis guaranteed. To meet the published specifications and avoidjitter-induced noise, the clock source driving the CLK inputmust exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in2.3 THE CLOCK INPUTS.
It is good practice to keep the ADC input clock line as shortas possible, to keep it well away from any other signals andto treat it as a transmission line. Other signals can introducejitter into the input clock signal. The clock signal can also in-troduce noise into the analog path if not isolated from thatpath.
Best dynamic performance is obtained when the exposed padat the back of the package has a good connection to ground.This is because this path from the die to ground is a lowerimpedance than offered by the package pins.
2.9 USING THE SERIAL INTERFACE
The ADC08D1520 may be operated in the Non-extendedControl Mode or in the Extended Control Mode. Table 10 andTable 11 describe the functions of pins 3, 4, 14 and 127 in theNon-extended Control Mode and the Extended Control Mode,respectively.
2.9.1 Non-Extended Control Mode Operation
Non-extended Control Mode operation means that the SerialInterface is not active and all controllable functions are con-trolled with various pin settings. Pin 41 is the primary controlof the Extended Control Mode enable function. When pin 41is logic high, the device is in the Non-extended Control Mode.If pin 41 is floating and pin 52 is floating or logic high, theExtended Control Enable function is controlled by pin 14. Thedevice has functions which are pin programmable when in theNon-extended Control Mode. An example is the full-scalerange; it is controlled in the Non-extended Control Mode bysetting pin 14 logic high or low. Table 10 indicates the pinfunctions of the ADC08D1520 in the Non-extended ControlMode.
TABLE 10. Non-Extended Control Mode Operation(Pin 41 Floating and Pin 52 Floating or Logic High)Pin3412714
LowReduced VODOutEdge = NegCalDly ShortReduced VIN
HighNormal VODOutEdge = PosCalDly LongNormal VIN
FloatingN/ADDRDESExtendedControlMode
Pin 3 can be either logic high or low in the Non-extendedControl Mode. Pin 14 must not be left floating to select thismode. See 1.2 NON-EXTENDED AND EXTENDED CON-TROL MODE for more information.
Pin 4 can be logic high, logic low or left floating in the Non-extended Control Mode. In the Non-extended Control Mode,pin 4 logic high or low defines the edge at which the outputdata transitions. See 2.4.3 Output Edge Synchronization formore information. If this pin is floating, the output Data Clock(DCLK) is a Double Data Rate (DDR) clock (see 1.1.5.3 Dou-ble Data Rate and Single Data Rate) and the output edgesynchronization is irrelevant since data is clocked out on bothDCLK edges.
Pin 127, if it is logic high or low in the Non-extended ControlMode, sets the calibration delay. If pin 127 is floating, the cal-ibration delay is short and the converter performs in DESMode.
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ADC08D1520TABLE 11. Extended Control Mode Operation
(Pin 41 Logic Low or Pin 14 Floating and Pin 52 Floating
or Logic High)
Pin34127
FunctionSCLK (Serial Clock)SDATA (Serial Data)SCS (Serial Interface Chip Select)2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-ed control mode. When using the serial interface, all nineaddress locations must be written at least once with the de-fault or desired values before calibration and subsequent useof the ADC.
Driving the inputs (analog or digital) beyond the powersupply rails. For device reliability, no input should go morethan 150 mV below the ground pins or 150 mV above thesupply pins. Exceeding these limits on even a transient basismay not only cause faulty or erratic operation, but may impairdevice reliability. It is not uncommon for high speed digitalcircuits to exhibit undershoot that goes more than a volt belowground. Controlling the impedance of high speed lines andterminating these lines in their characteristic impedanceshould control overshoot.
Care should be taken not to overdrive the inputs of theADC08D1520. Such practice may lead to conversion inaccu-racies and even to device damage.
Incorrect analog input common mode voltage in the d.c.coupled mode. As discussed in 1.1.4 The Analog Inputs and2.2 THE ANALOG INPUT, the Input common mode voltagemust remain within 50 mV of the VCMO output , which varieswith temperature and must also be tracked. Distortion perfor-mance will be degraded if the input common mode voltage ismore than 50 mV from VCMO .
Using an inadequate amplifier to drive the analog input.Use care when choosing a high frequency amplifier to drivethe ADC08D1520 as many high speed amplifiers will havehigher distortion than the ADC08D1520, resulting in overallsystem performance degradation.
Driving the VBG pin to change the reference voltage. Asmentioned in 2.1 THE REFERENCE VOLTAGE, the refer-ence voltage is intended to be fixed by FSR pin or Full-ScaleVoltage Adjust register settings. Over driving this pin will notchange the full scale value, but can be used to change theLVDS common mode voltage from 0.8V to 1.2V by tying theVBG pin to VA.
Driving the clock input with an excessively high levelsignal. The ADC input clock level should not exceed the leveldescribed in the Operating Ratings Table or the input offsetcould change.
Inadequate input clock levels. As described in 2.3 THECLOCK INPUTS, insufficient input clock levels can result inpoor performance. Excessive input clock levels could resultin the introduction of an input offset.
Using a clock source with excessive jitter, using an ex-cessively long input clock signal trace, or having othersignals coupled to the input clock signal trace. This willcause the sampling interval to vary, causing excessive outputnoise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in2.6.2 Thermal Management, it is important to provide ade-quate heat removal to ensure device reliability. This can bedone either with adequate air flow or the use of a simple heatsink built into the board. The backside pad should be ground-ed for best performance.
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ADC08D1520Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.
128-Lead Exposed Pad LQFPOrder Number ADC08D1520CIYBNS Package Number VNX128A
43www.national.com
ADC08D1520 Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D ConverterNotes
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