AD8328-EVAL资料

FEATURES

Supports DOCSIS and EuroDOCSIS standards for reverse path transmission systems

Gain programmable in 1 dB steps over a 59 dB range Low distortion at 60 dBmV output −57.5 dBc SFDR at 21 MHz − dBc SFDR at 65 MHz

Output noise level @ minimum gain 1.2 nV/√Hz Maintains 300 Ω output impedance Tx-enable and Tx-disable condition

Upper bandwidth: 107 MHz (full gain range) 5 V supply operation Supports SPI interfaces

APPLICATIONS

DOCSIS and EuroDOCSIS cable modems CATV set-top boxes

CATV telephony modems

Coaxial and twisted pair line drivers

GENERAL DESCRIPTION

The AD83281 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8328 ideally suited for MCNS-DOCSIS and EuroDOCSIS applications. The gain of the AD8328 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB.

The AD8328 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 2:1 transformer.

Distortion performance of −53 dBc is achieved with an output level up to 60 dBmV at 65 MHz bandwidth over a wide temperature range.

This device has a sleep mode function that reduces the quiescent current to 2.6 mA and a full power-down function that reduces power-down current to 20 μA.

The AD8328 is packaged in a low cost 20-lead LFCSP and

a 20-lead QSOP. The AD8328 operates from a single 5 V supply and has an operational temperature range of −40°C to +85°C.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

5 V Upstream Cable Line Driver

AD8328

FUNCTIONAL BLOCK DIAGRAM

BYPAD8328VIN+

DIFFORVOUT+SINGLEATTENUATIONPOWERINPUTVERNIERAMPVAMPCOREIN–

VOUT–8ZOUT DIFF =ZIN (SINGLE) = 800Ω300ΩZIN (DIFF) = 1.6kΩDECODE8POWER-DOWNDATA LATCHLOGICRAMP8SHIFTREGISTER100-851GNDDATENSDATACLKTXENSLEEP

30

Figure 1.

–50–52VOUT = 60dBmV–@ MAX GAIN,THIRD HARMONIC)–56Bcd( –58NOIT–60ROTS–62IVDOUT = 60dBmV–@ MAX GAIN,SECOND HARMONIC–66–68200-851–703051525355565FREQUENCY (MHz)

Figure 2. Worst Harmonic Distortion vs. Frequency

1

Patent pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

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AD8328

Signal Integrity Layout Considerations...................................11 Initial Power-Up.........................................................................12 RAMP Pin and BYP Pin Features............................................12 Transmit Enable (TXEN) and SLEEP......................................12 Distortion, Adjacent Channel Power, and DOCSIS..............12 Noise and DOCSIS.....................................................................12 Evaluation Board Features and Operation..............................12 Differential Signal Source.........................................................13 Differential Signal from Single-Ended Source.......................13 Single-Ended Source..................................................................13 Overshoot on PC Printer Ports................................................13 Installing Visual Basic Control Software.................................13 Running AD8328 Software.......................................................14 Controlling Gain/Attenuation of the AD8328.......................14 Transmit Enable and Sleep Mode.............................................14 Memory Functions.....................................................................14 Outline Dimensions.......................................................................17 Ordering Guide...............................................................................18

TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Logic Inputs (TTL-/CMOS-Compatible Logic).......................4 Timing Requirements..................................................................4 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configurations and Function Descriptions...........................7 Typical Performance Characteristics.............................................8 Applications.....................................................................................10 General Applications..................................................................10 Circuit Description.....................................................................10 SPI Programming and Gain Adjustment................................10 Input Bias, Impedance, and Termination................................10 Output Bias, Impedance, and Termination.............................10 Power Supply...............................................................................11

REVISION HISTORY

10/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal Changes to Table 4............................................................................6 Updated Outline Dimensions.......................................................17 Changes to Ordering Guide..........................................................18

11/02—Revision 0: Initial Version

Rev. A | Page 2 of 20

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AD8328

SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = RIN = 75 Ω, VIN (differential) = 29 dBmV. The AD8328 is characterized using a 2:1 transformer1 at the device output. Table 1. Parameter INPUT CHARACTERISTICS Specified AC Voltage Input Resistance Input Capacitance GAIN CONTROL INTERFACE Voltage Gain Range Maximum Gain Minimum Gain Output Step Size Output Step Size Temperature Coefficient OUTPUT CHARACTERISTICS Bandwidth (−3 dB) Bandwidth Roll-Off 1 dB Compression Point2 Output Noise2 Maximum Gain Minimum Gain Tx Disable Noise Figure2 Maximum Gain Differential Output Impedance OVERALL PERFORMANCE Second-Order Harmonic Distortion4, 5 Third-Order Harmonic Distortion4, 5 ACPR2, 6 Isolation (Tx Disable)2 POWER CONTROL Tx Enable Settling Time Tx Disable Settling Time Output Switching Transients2 Output Settling Due to Gain Change Due to Input Step Change POWER SUPPLY Operating Range Quiescent Current OPERATING TEMPERATURE RANGE Conditions Output = 60 dBmV, max gain Single-ended input Differential input Gain code = 60 decimal codes Gain code = 1 decimal code TA = −40°C to +85°C All gain codes (1 to 60 decimal codes) f = 65 MHz Maximum gain, f = 10 MHz, output referred Minimum gain, f = 10 MHz, input referred f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz Tx enable and Tx disable f = 33 MHz, VOUT = 60 dBmV @ maximum gain f = 65 MHz, VOUT = 60 dBmV @ maximum gain f = 21 MHz, VOUT = 60 dBmV @ maximum gain f = 65 MHz, VOUT = 60 dBmV @ maximum gain Maximum gain, f = 65 MHz Maximum gain, VIN = 0 Maximum gain, VIN = 0 Equivalent output = 31 dBmV Equivalent output = 61 dBmV Minimum to maximum gain Maximum gain, VIN = 29 dBmV Maximum gain Minimum gain Tx disable (TXEN = 0) SLEEP mode (power-down) Min Typ Max Unit 29 dBmV 800 Ω 1600 Ω 2 pF 58 59.0 60 dB 30.5 31.5 32.5 dB −28.5 −27.5 −26.5 dB 0.6 1.0 1.4 dB/LSB ±0.0005 dB/°C 107 MHz 1.2 dB 17.9 18.4 dBm 2.2 3.3 dBm 135 151 nV/√Hz 1.2 1.3 nV/√Hz 1.1 1.2 nV/√Hz 16.7 17.7 dB 75 ± 30%3 Ω −67 −56 dBc −61 −55 dBc −57.5 −56 dBc − −52.5 dBc −58 −56 dBc −85 −81 dB 2.5 μs 3.8 μs 2.5 6 mV p-p 16 mV p-p 60 ns 30 ns 4.75 5 5.25 V 98 120 140 mA 18 26 34 mA 1 2.6 3.5 mA 1 20 100 μA −40 +85 °C

Rev. A | Page 3 of 20

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AD8328

TOKO 458 PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz. Guaranteed by design and characterization to ±4 sigma for TA = 25°C. 3

Measured through a 2:1 transformer. 4

Specification is worst case over all gain codes. 5

Guaranteed by design and characterization to ±3 sigma for TA = 25°C. 6

VIN = 29 dBmV, QPSK modulation, 160 kSPS symbol rate.

12

LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)

DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V; full temperature range. Table 2. Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current (VINH = 5 V) CLK, SDATA, DATENLogic 0 Current (VINL = 0 V) CLK, SDATA, DATENLogic 1 Current (VINH = 5 V) TXEN Logic 0 Current (VINL = 0 V) TXEN Logic 1 Current (VINH = 5 V) SLEEPLogic 0 Current (VINL = 0 V) SLEEPMin Typ Max Unit 2.1 5.0 V 0 0.8 V 0 20 nA –600 –100 nA 50 190 μA −250 −30 μA 50 190 μA −250 −30 μA

TIMING REQUIREMENTS

Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Clock Pulse Width (tWH) 16.0 ns Clock Period (tC) 32.0 ns Setup Time SDATA vs. Clock (tDS) 5.0 ns 15.0 ns Setup Time DATEN vs. Clock (tES) Hold Time SDATA vs. Clock (tDH) 5.0 ns 3.0 ns Hold Time DATEN vs. Clock (tEH) 10 ns Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)

Rev. A | Page 4 of 20

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AD8328

tDSSDATAVALID DATA-WORD G1MSB. . . .LSBVALID DATA-WORD G2

tCtWHCLKtESDATENtEH8 CLOCK CYCLESGAIN TRANSFER (G1)GAIN TRANSFER (G2)tOFFTXENtGStON03158-003ANALOGOUTPUTSIGNAL AMPLITUDE (p-p)

Figure 3. Serial Interface Timing

VALID DATA BITSDATAMSBMSB-1MSB-2tDStDH03158-004CLK Figure 4. SDATA Timing

Rev. A | Page 5 of 20

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AD8328

ABSOLUTE MAXIMUM RATINGS

Table 4. Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage VCC 6 V rating only; functional operation of the device at these or any Input Voltage other conditions above those indicated in the operational VIN+, VIN− 1.5 V p-p section of this specification is not implied. Exposure to absolute

−0.8 V to +5.5 V DATEN, SDATA, CLK, SLEEP, TXEN maximum rating conditions for extended periods may affect

Stresses above those listed under Absolute Maximum Ratings

Internal Power Dissipation device reliability.

QSOP (θJA = 83.2°C/W)1700 mW LFCSP (θJA = 30.4°C/W)2700 mW Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering 60 sec 300°C 1 Thermal resistance measured on SEMI standard 4-layer board.

2

Thermal resistance measured on SEMI standard 4-layer board, paddle soldered to board.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 6 of 20

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AD8328

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GNDVCCGNDGND1VCCGNDGNDVIN+VIN–DATENSDATA23456201918GNDVCCTXENRAMPVOUT+GND1GND2VIN+3VIN–4GND5201918171615RAMPAD83281716VCCTXENTOP VIEW(Not to Scale)15VOUT–14131211AD8328TOP VIEW(Not to Scale)14VOUT+13VOUT–12BYP11NCGND7BYPNCDATENSDATASLEEPCLKGND03158-005CLK10GND03158-006SLEEP6710

Figure 5. 20-Lead QSOP Pin Configuration

NC = NO CONNECT

Figure 6. 20-Lead LFCSP Pin Configuration

Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions MPin No. Pin No. 20-Lead 20-Lead Description QSOP LFCSP nemonic Common External Ground Reference. 1, 3, 4, 7, 1, 2, 5, 9, GND 11, 20 18, 19 2, 19 17, 20 VCC Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin. 5 3 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. 6 4 VIN− Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. 8 6 DATENData Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 9 7 SDATA Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the most significant bit (MSB) first. 10 8 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. 12 10 SLEEPLow Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA. A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part. 13 11 NC No Connect. 14 12 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor). 15 13 VOUT− Negative Output Signal 16 14 VOUT+ Positive Output Signal 17 15 RAMP External RAMP Capacitor (Optional) 18 16 TXEN Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.

Rev. A | Page 7 of 20

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AD8328

TYPICAL PERFORMANCE CHARACTERISTICS

–55–50VOUT = 61dBmV@ MAX GAIN–60DISTORTION (dBc)VOUT = 60dBmV@ MAX GAIN–55–65DISTORTION (dBc)VOUT = 61dBmV@ MAX GAINVOUT = 60dBmV@ MAX GAIN–60VOUT = 59dBmV@ MAX GAIN–65–7003158-007VOUT = 59dBmV@ MAX GAIN–755152535FREQUENCY (MHz)5565–70515

2535FREQUENCY (MHz)556503158-010

Figure 7. Second-Order Harmonic Distortion vs.

Frequency for Various Output Powers

–50VOUT = 60dBmV@ MAX GAIN–50Figure 10. Third-Order Harmonic Distortion vs.

Frequency for Various Output Powers

VOUT = 60dBmV@ MAX GAINTA = +85°C–55DISTORTION (dBc)TA = +25°CTA = –40°CDISTORTION (dBc)–55–60TA = +25°C–65TA = +85°C03158-008TA = –40°C–60–70–7551525355565–65515

Figure 8. Second-Order Harmonic Distortion vs. Frequency vs. Temperature

100CHPWRACP60dBmV–58.2dBFREQUENCY (MHz)

Figure 11. Third-Order Harmonic Distortion vs. Frequency vs. Temperature

605040302535FREQUENCY (MHz)5565VOUT = 57dBmV/TONE@ MAX GAIN–10–20VOUT (dBmV)POUT (dBm)–30–40–50–60–70–80–90c11c11cu1C0C003158-00920100–10–20–30cu103158-01275kHz/DIVSPAN 750kHz

–4041.1.741.8Figure 9. Adjacent Channel Power

41.942.042.142.2FREQUENCY (MHz)42.342.442.5Figure 12. Two-Tone Intermodulation Distortion

Rev. A | Page 8 of 20

03158-011

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40302010DEC60DECISOLATION (dB)AD8328

0–10–20–30–40–50–60–70–8003158-013TXEN = 0VIN = 29dBmVGAIN (dB)DEC480DEC42DEC36–10DEC30DEC24–20–30DEC18DEC12DEC 1 TO DEC 6110100FREQUENCY (MHz)MAX GAINMIN GAIN03158-016–90–100–400.110001101001000

FREQUENCY (MHz)Figure 13. AC Response

1.4f = 10MHz1.2

Figure 16. Isolation in Transmit Disable Mode vs. Frequency

1.61.20.8OUTPUT STEP SIZE (dB)GAIN ERROR (dB)0.40–0.4f = 10MHzf = 5MHzf = 42MHz1.00.803158-014–0.803158-017–1.2–1.6f = 65MHz06121824303248600.60612182430324860GAIN CONTROL (Decimal Code)

GAIN CONTROL (Decimal Code)Figure 14. Output Step Size vs. Gain Control

140OUTPUT REFERRED VOLTAGE NOISE (nV/√Hz)

Figure 17. Gain Error vs. Gain Control

130120QUIESCENT SUPPLY CURRENT (mA)f = 10MHzTXEN = 112010080604020006121824303248GAIN CONTROL (Decimal Code)601101009080706050403020010203040GAIN CONTROL (Decimal Code)506003158-01803158-015

Figure 15. Output Referred Voltage Noise vs. Gain Control

Figure 18. Supply Current vs. Gain Control

Rev. A | Page 9 of 20

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AD8328

SPI PROGRAMMING AND GAIN ADJUSTMENT

The AD8328 is controlled through a serial peripheral interface (SPI) of three digital data lines: CLK, DATEN, and SDATA. Changing the gain requires eight bits of data to be streamed into the SDATA port. The sequence of loading the SDATA register begins on the falling edge of the DATEN pin, which activates the CLK line. With the CLK line activated, data on the SDATA line is clocked into the serial shift register on the rising edge of the CLK pulses, MSB first. The 8-bit data-word is latched into the attenuator core on the rising edge of the DATEN line. This provides control over the changes in the output signal level. The serial interface timing for the AD8328 is shown in Figure 3 and Figure 4. The programmable gain range of the AD8328 is −28 dB to +31 dB with steps of 1 dB per least significant bit (LSB). This provides a total gain range of 59 dB. The AD8328 was characterized with a differential signal on the input and a TOKO 458PT-1087 2:1 transformer on the output. The AD8328 incorporates supply current scaling with gain code, as shown in Figure 18. This allows reduced power consumption when operating in lower gain codes.

APPLICATIONS

GENERAL APPLICATIONS

The AD8328 is primarily intended for use as the power

amplifier (PA) in Data Over Cable Service Interface Specification (DOCSIS)-certified cable modems and CATV set-top boxes. The upstream signal is either a QPSK or QAM signal generated by a DSP, a dedicated QPSK/QAM modulator, or a DAC. In all cases, the signal must be low-pass filtered before being applied to the PA to filter out-of-band noise and higher order harmonics from the amplified signal.

Due to the varying distances between the cable modem and the head-end, the upstream PA must be capable of varying the output power by applying gain or attenuation. The ability to vary the output power of the AD8328 ensures that the signal from the cable modem has the proper level once it arrives at the head-end. The upstream signal path commonly includes a diplexer and cable splitters. The AD8328 has been designed to overcome losses associated with these passive components in the upstream cable path.

CIRCUIT DESCRIPTION

The AD8328 is composed of three analog functions in the power-up or forward mode. The input amplifier (preamp) can be used single-ended or differentially. If the input is used in the differential configuration, it is imperative that the input signals be 180° out of phase and of equal amplitude. A vernier is used in the input stage for controlling the fine 1 dB gain steps. This stage then drives a DAC, which provides the bulk of the

AD8328’s attenuation. The signals in the preamp and DAC gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage. The output stage maintains 300 Ω differential output impedance, which maintains proper match to 75 Ω when used with a 2:1 balun transformer.

5VINPUT BIAS, IMPEDANCE, AND TERMINATION

The VIN+ and VIN− inputs have a dc bias level of VCC/2; therefore, the input signal should be ac-coupled as shown in Figure 20. The differential input impedance of the AD8328 is approximately 1.6 kΩ, while the single-ended input is 800 Ω. The high input impedance of the AD8328 allows flexibility in termination and properly matching filter networks. The AD8328 exhibits optimum performance when driven with a pure differential signal.

OUTPUT BIAS, IMPEDANCE, AND TERMINATION

The output stage of the AD8328 requires a bias of 5 V. The 5 V power supply should be connected to the center tap of the output transformer. In addition, the VCC applied to the center tap of the transformer should be decoupled as seen in Figure 20.

VCCVIN+VOUT+AD8328VOUT–RL1V2IN1V2INVIN–BYPGND03158-019

Figure 19. Characterization Circuit

Rev. A | Page 10 of 20

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VCCAD8328

10µF1AD8328QSOP0.1µFVIN+ZIN = 150Ω165Ω0.1µFVIN–DATENSDATACLKTXENSLEEP1kΩ1kΩ1kΩGND2VCC3GND4GND5VIN+6VIN–7GND8DATEN9SDATA10CLK20GND19VCC18TXEN17RAMP16VOUT+15VOUT–14BYP13NC0.1μF12SLEEP11GND0.1μFTO DIPLEXERZIN = 75ΩTOKO 458PT-10870.1μF1kΩ03158-0201kΩ

Figure 20. Typical Application Circuit

Table 6. Adjacent Channel Power

Channel Symbol Rate (kSym/s) 160 320 0 1280 2560 5120

Adjacent Channel Symbol Rate (kSym/s) 160 320 0 1280

−58 −60 −63 −66 −58 −59 −60 − −60 −58 −59 −61 −62 −60 −59 −60 − −62 −60 −59 −66 −65 −62 −61 2560

−66 −66 − −61 −60 −59

5120

− −65 −65 −63 −61 −60

The output impedance of the AD8328 is 300 Ω, regardless of whether the amplifier is in transmit enable or transmit disable mode. This, when combined with a 2:1 voltage ratio (4:1 impedance ratio) transformer, eliminates the need for

external back termination resistors. If the output signal is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad must be used to provide the test circuit with the proper impedance match. The AD8328 evaluation board provides a convenient means to implement a matching attenuator. Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in the R16 placeholder allows testing on a 50 Ω system. When using a matching attenuator, it should be noted that there is a 5.7 dB of power loss (7.5 dB voltage) through the network.

AD8328 and the output transformer. All AD8328 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes.

SIGNAL INTEGRITY LAYOUT CONSIDERATIONS

Careful attention to printed circuit board layout details will prevent problems due to board parasitics. Proper RF design techniques are mandatory. The differential input and output traces should be kept as short as possible. Keeping the traces short minimizes parasitic capacitance and inductance. This is most critical between the outputs of the AD8328 and the 2:1 output transformer. It is also critical that all differential signal paths be symmetrical in length and width. In addition, the input and output traces should be adequately spaced to

minimize coupling (crosstalk) through the board. Following these guidelines optimizes the overall performance of the AD8328 in all applications.

POWER SUPPLY

The 5 V supply should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground using a 10 μF tantalum capacitor located close to the AD8328. In

addition to the 10 μF capacitor, each VCC pin should be individually decoupled to ground with ceramic chip capacitors located close to the pins. The bypass pin, BYP, should also be decoupled. The PCB should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the

Rev. A | Page 11 of 20

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AD8328

various output power levels. These figures are useful for determining the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency (above 42 MHz for DOCSIS and above 65 MHz for EuroDOCSIS) are sharply attenuated by the low-pass filter function of the diplexer. Another measure of signal integrity is adjacent channel power, commonly referred to as ACP. DOCSIS 2.0, Section 6.2.21.1.1 states, “Spurious emissions from a transmitted carrier may

occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates.” Figure 9 shows the

measured ACP for a 60 dBmV QPSK signal taken at the output of the AD8328 evaluation board. The transmit channel width and adjacent channel width in Figure 9 correspond to the symbol rates of 160 kSym/s. Table 6 shows the ACP results for the AD8328 driving a QPSK 60 dBmV signal for all conditions in DOCSIS Table 6-9, Adjacent Channel Spurious Emissions.

INITIAL POWER-UP

When the supply voltage is first applied to the AD8328, the gain of the amplifier is initially set to Gain Code 1. Since power is first applied to the amplifier, the TXEN pin should be held low (Logic 0) to prevent forward signal transmission. After power is applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the SPI Programming and Gain Adjustment section. The TXEN pin can then be brought from Logic 0 to Logic 1, enabling forward signal transmission at the desired gain level.

RAMP PIN AND BYP PIN FEATURES

The RAMP pin is used to control the length of the burst on and off transients. By default, leaving the RAMP pin unconnected results in a transient that is fully compliant with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients. DOCSIS requires that all between-burst transients must be dissipated no faster than 2 μs; and adding capacitance to the RAMP pin adds more time to the transient.

The BYP pin is used to decouple the output stage at midsupply. Typically, for normal DOCSIS operation, the BYP pin should be decoupled to ground with a 0.1 μF capacitor. However, in

applications that require transient on/off times faster than 2 μs, smaller capacitors can be used, but it should be noted that the BYP pin should always be decoupled to ground.

NOISE AND DOCSIS

At minimum gain, the AD8328 output noise spectral density is 1.2 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious Emissions in 5 MHz to 42 MHz, specifies the output noise for various symbol rates. The calculated noise power in dBmV for 160 kSym/s is

⎡⎛1.2nV2⎞⎤

⎞⎟⎥+60=−66.4dBmV (1) ⎢20×log⎜⎛160kHz×⎜⎟⎜⎟⎢⎜⎝Hz⎠⎟⎥

⎝⎠⎦⎣

TRANSMIT ENABLE (TXEN) AND SLEEP The asynchronous TXEN pin is used to place the AD8328 into

between-burst mode. In this reduced current state, the output impedance of 75 Ω is maintained. Applying Logic 0 to the

TXEN pin deactivates the on-chip amplifier, providing a 97.8% reduction in consumed power. For 5 V operation, the supply current is typically reduced from 120 mA to 2.6 mA. In this mode of operation, between-burst noise is minimized and high input to output isolation is achieved. In addition to the TXEN pin, the AD8328 also incorporates an asynchronous SLEEP pin, which can be used to further reduce the supply current to

approximately 20 μA. Applying Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode can result in a transient voltage at the output of the amplifier.

Comparing the computed noise power of −66.4 dBmV to the +8 dBmV signal yields −74.4 dBc, which meets the required level set forth in DOCSIS Table 6-10. As the AD8328 gain is increased above this minimum value, the output signal

increases at a faster rate than the noise, resulting in a signal- to-noise ratio that improves with gain. In transmit disable mode, the output noise spectral density is 1.1 nV/√Hz, which results in −67 dBmV when computed over 160 kSym/s. The noise power was measured directly at the output of the AD8328AR-EVAL board.

EVALUATION BOARD FEATURES AND OPERATION

The AD8328 evaluation board and control software can be used to control the AD8328 upstream cable driver via the parallel port of a PC. A standard printer cable connected to the parallel port of the PC is used to feed all the necessary data to the AD8328 using the Windows®-based control software. This package

provides a means of controlling the gain and the power mode of the AD8328. With this evaluation kit, the AD8328 can be evaluated in either a single-ended or differential input configuration. See Figure 26 for a schematic of the evaluation board.

DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS

To deliver the DOCSIS required 58 dBmV of QPSK signal and 55 dBmV of 16 QAM signal, the PA is required to deliver up to 60 dBmV. This added power is required to compensate for

losses associated with the diplex filter or other passive components that may be included in the upstream path of cable modems or set-top boxes. It should be noted that the AD8328 was characterized with a differential input signal. Figure 7 and Figure 10 show the AD8328 second and third harmonic distortion performance vs. the fundamental frequency for

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AD8328

requires the removal of R2 and R3 to be shorted with R4 open, as well as the addition of 82.5 Ω at R1 and 39.2 Ω at R17 for 75 Ω termination. Table 7 shows the correct values for R11 and R12 for some common input configurations. Other input impedance configurations can be accommodated using Equation 4 and Equation 5.

DIFFERENTIAL SIGNAL SOURCE

Typical applications for the AD8328 use a differential input signal from a modulator or a DAC. See Table 7 for common values of R4, or calculate other input configurations using Equation 2. This circuit configuration will give optimal distortion results due to the symmetric input signals. Note that this configuration was used to characterize the AD8328.

ZIN×800

(4) −Z800INZ×1.6kΩ

(2) R4=IN

Z×R11.6kΩ−ZIN

(5) R17=IN

R1+ZIN

R1=

VIN+ZINVIN–R4AD832803158-021VIN+R1 ZINAD8328R1703158-023Figure 21. Differential Circuit

DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE

The default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. This configuration uses a 1:1 balun transformer to approximate a differential signal. Because of the nonideal nature of real transformers, the differential signal is not purely equal and opposite in amplitude. Although this circuit slightly sacrifices even-order harmonic distortion due to asymmetry, it does provide a convenient way to evaluate the AD8328 with a single-ended source.

The AD8328 evaluation board is populated with a TOKO 617DB-A0070 1:1 for this purpose (T1). Table 7 provides

typical R4 values for common input configurations. Other input impedances can be calculated using Equation 3. See Figure 26 for a schematic of the evaluation board. To use the transformer for converting a single-ended source into a differential signal, the input signal must be applied to VIN+.

Figure 23. Single-Ended Circuit

Table 7. Common Matching Resistors

Differential Input Termination

ZIN (Ω) R2/R3 R4 (Ω) R1/R17 50 Open 51.1 Open/Open 75 Open 78.7 Open/Open 100 Open 107.0 Open/Open 150 Open 165.0 Open/Open

Single-Ended Input Termination

ZIN (Ω) R2 (Ω)/R3 (Ω) R4 (Ω) R1 (Ω)/R17 (Ω) 50 0/0 Open 53.6/25.5 75 0/0 Open 82.5/39.2

OVERSHOOT ON PC PRINTER PORTS

The data lines on some PC parallel printer ports have excessive overshoot that can cause communication problems when presented to the CLK pin of the AD8328. The evaluation board was designed to accommodate a series resistor and shunt capacitor (R2 and C5 in Figure 26) to filter the CLK ZIN×1.6kΩ

(3) R4=signal if required.

1.6kΩ−ZIN

VIN+03158-022INSTALLING VISUAL BASIC CONTROL SOFTWARE

R4ZINAD8328

Figure 22. Single-to-Differential Circuit

SINGLE-ENDED SOURCE

Although the AD8328 was designed to have optimal DOCSIS performance when used with a differential input signal, the AD8328 can also be used as a single-ended receiver, or an IF digitally controlled amplifier. However, as with the single-ended-to-differential configuration previously noted, even-order harmonic distortion is slightly degraded.

When operating the AD8328 in a single-ended input mode, VIN+ and VIN– should be terminated as shown in Figure 23. On the AD8328 evaluation boards, this termination method

Install the CabDrive_28 software by running the setup.exe file on Disk One of the AD8328 evaluation software. Follow the on-screen directions and insert Disk Two when prompted. Choose the installation directory and then select the icon in the upper left to complete the installation.

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AD8328

TRANSMIT ENABLE AND SLEEP MODE

The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8328 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmission. The Transmit Enable button applies Logic 1 to the TXEN pin, enabling the AD8328 for forward transmission. Checking the Enable SLEEP Mode box applies Logic 0 to the asynchronous SLEEP pin, setting the AD8328 for SLEEP mode.

RUNNING AD8328 SOFTWARE

To load the control software, go to Start, Programs, CABDRIVE_28 or select the AD8328.exe file from the installed directory. Once loaded, select the proper parallel port to communicate with the AD8328 (see Figure 24).

MEMORY FUNCTIONS

The Memory section of the software provides a way to alternate between two gain settings. The X→M1 button stores the current value of the GAIN SLIDER into memory, while the RM1 button recalls the stored value, returning the gain SLIDER to the stored level. The same applies to the X→M2 and RM2 buttons.

03158-024

Figure 24. Parallel Port Selection

CONTROLLING GAIN/ATTENUATION OF THE AD8328

The SLIDER controls the gain/attenuation of the AD8328, which is displayed in dB and in V/V. The gain scales 1 dB per LSB. The gain code from the position of the SLIDER is displayed in decimal, binary, and hexadecimal (see Figure 25).

03158-025

Figure 25. Control Software Interface

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VIN+_AR1R2T1TOKO617DB-A0070C1A0.1µFTP9R478.7ΩC2A0.1μF123AD8328

GNDVCCGNDGNDVIN+VIN–GNDDATENSDATACLKQSOPGNDVCCTXENRAMPVOUT+VOUT–BYPNCSLEEPGND20191817161514131211C9 0.1µFC810µFVCCVIN–_AR17R51kΩC3TP1R3C10 0.1µF4P1 2R60Ω5678C11TOKOR158PT-10870ΩC12 0.1µFVCC112346CABLE_OAR16P1 3R71kΩTP2R80Ω910C4TP3AD8328C130.1µFP1 5R91kΩR100ΩTP10TP11C5P1 6R111kΩC6TP4R120ΩTP_AGND1AGND1TP12TP_VCC1VCC1P1 7P1 16R131kΩC7TP5P1 19P1 20P1 21P1 22P1 23P1 24P1 25P1 26P1 27P1 28P1 29P1 30P1 33R140Ω03158-026 Figure 26. AD8328 Evaluation Board Schematic

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AD8328

03158-027

Figure 30. Internal Ground Plane

03158-030

Figure 27. Primary Side

03158-028

Figure 31. Secondary Side

03158-031

Figure 28. Component Side Silkscreen

03158-02903158-032

Figure 29. Internal Power Plane

Figure 32. Secondary Side Silkscreen

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AD8328

OUTLINE DIMENSIONS

4.00BSC SQ0.60MAXPIN 1INDICATORTOPVIEW3.75BCS SQ0.750.550.350.05 MAX0.02 NOM0.50BSC0.20REFCOPLANARITY0.081110650.60MAX1615PIN 1INDICATOR2012.252.10 SQ1.950.25 MIN0.300.230.181.000.850.80SEATINGPLANE12° MAX0.80 MAX0.65 TYPCOMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 33. 20-Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

0.3450.3410.33720110.1580.10.1501100.2440.2360.228PIN 10.0650.0490.0690.0538°0°0.0100.004COPLANARITY0.0040.025BSC0.0120.008SEATINGPLANE0.0100.0060.0500.016COMPLIANT TO JEDEC STANDARDS MO-137-AD

Figure 34. 20-Lead Shrink Small Outline Package [QSOP]

(RQ-20)

Dimensions shown in inches

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AD8328

ORDERING GUIDE

Model Temperature Range AD8328ARQ –40°C to +85°C AD8328ARQ-REEL –40°C to +85°C AD8328ARQZ1–40°C to +85°C

1

AD8328ARQZ-REEL–40°C to +85°C AD8328ACP –40°C to +85°C AD8328ACP-REEL –40°C to +85°C AD8328ACP-REEL7 –40°C to +85°C AD8328ACPZ1–40°C to +85°C

1

AD8328ACPZ-REEL–40°C to +85°C AD8328ACPZ-REEL71–40°C to +85°C AD8328ACP-EVAL AD8328ARQ-EVAL

1

Package Description 20-Lead QSOP 20-Lead QSOP 20-Lead QSOP 20-Lead QSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ

Evaluation Board Evaluation Board Package Option

RQ-20 RQ-20 RQ-20 RQ-20 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1

Z = Pb-free part.

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AD8328

NOTES

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AD8328

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03158–0–10/05(A)

Rev. A | Page 20 of 20