Process for fabricating a semiconductor integrated

专利名称：Process for fabricating a semiconductor

integrated circuit utilizing an exposuremethod

发明人：Shuji Nakao申请号：US08/799595申请日：19970212公开号：US06162736A公开日：20001219

摘要：In a method of manufacturing a semiconductor device, a plurality of inter layerconductive path is formed through a first resist pattern which in turn is formed by anexposure of a hole pattern mask. A plurality of conductive lines is formed, adjacent to thelayer of the conductive paths, through a second resist pattern which in turn is formed bydouble exposure of a line pattern mask and the hole pattern mask. Each conductive lineis positioned on at least one of the conductive paths. Or alternatively, each conductivepath is positioned between the lines.

申请人：MITSUBISHI DENKI KABUSHIKI KAISHA

代理机构：Oblon, Spivak, McClelland, Maier & Neustadt, P

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