PDU138-20资料

PDU138

3-BIT PROGRAMMABLEDELAY LINE(SERIES PDU138)FEATURES

• Digitally programmable in 8 delay steps• Monotonic delay-versus-address variation• Precise and stable delays

• Input & outputs fully TTL interfaced & buffered

2

• 10 TL fan-out capability

• Fits standard 16-pin DIP socket• Auto-insertable

N/CN/CN/CINOUTN/CEN/GND

data3®delaydevices, inc.PACKAGES

12345678

161514131211109

VCCN/CN/CN/CN/CA0A1A2

PDU138-xxPDU138-xxMDIP

Military DIP

FUNCTIONAL DESCRIPTION

The PDU138-series device is a 3-bit digitally programmable delay line.The delay, TDA, from the input pin (IN) to the output pin (OUT) depends onthe address code (A2-A0) according to the following formula:

TDA = TD0 + TINC * A

PIN DESCRIPTIONS

INOUTA2A1A0EN/VCCGND

Delay Line InputNon-inverted OutputAddress Bit 2Address Bit 1Address Bit 0Output Enable+5 VoltsGround

where A is the address code, TINC is the incremental delay of the device,and TD0 is the inherent delay of the device. The incremental delay isspecified by the dash number of the device and can range from 0.5ns

through 50ns, inclusively. The enable pin (EN/) is held LOW during normaloperation. When this signal is brought HIGH, OUT is forced into the LOW

state. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

• Total programmed delay tolerance: 5% or 1ns,

whichever is greater

• Inherent delay (TD0):7ns typical (OUT)• Setup time and propagation delay:

Address to input setup (TAIS):12ns typ.Disable to output delay (TDISO):12ns typ.

• Operating temperature: 0° to 70° C

• Temperature coefficient: 100PPM/°C (excludes TD0)• Supply voltage VCC: 5VDC ± 5%• Supply current:ICCH = 45ma

ICCL = 20ma

• Minimum pulse width: 20% of total delay

DASH NUMBER SPECIFICATIONS

PartNumberPDU138-.5PDU138-1PDU138-2PDU138-5PDU138-10PDU138-12PDU138-15PDU138-20PDU138-40PDU138-50

Incremental DelayPer Step (ns)

.5 ± .31 ± .42 ± .45 ± .610 ± 1.012 ± 1.215 ± 1.320 ± 1.540 ± 2.050 ± 2.5

Total DelayChange (ns)3.5 ± 1.07 ± 1.014 ± 1.035 ± 1.870 ± 3.584 ± 4.2105 ± 5.3140 ± 7.0280 ± 14.0350 ± 17.5

NOTE:Any dash number between .5 and 50 not

shown is also available.

©2002 Data Delay Devices

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PDU138

APPLICATION NOTES

ADDRESS UPDATE

The PDU138 is a memory device. As such,special precautions must be taken when

changing the delay address in order to preventspurious output signals. The timing restrictionsare shown in Figure 1.

After the last signal edge to be delayed has

appeared on the OUT pin, a minimum time, TOAX,is required before the address lines can change.This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new addresscodes, respectively. Violation of this constraintmay, depending on the history of the input signal,cause spurious signals to appear on the OUT pin.The possibility of spurious signals persists untilthe required TOAX has elapsed.

A similar situation occurs when using the EN/signal to disable the output while IN is active. Inthis case, the unit must be held in the disabledstate until the device is able to “clear” itself. Thisis achieved by holding the EN/ signal high and theIN signal low for a time given by:

TDISH = Ai * TINC

Violation of this constraint may, depending on thehistory of the input signal, cause spurious signalsto appear on the OUT pin. The possibility ofspurious signals persists until the required TDISHhas elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on inputpulse width and period listed in the AC

Characteristics table. The recommended

conditions are those for which the delay tolerancespecifications and monotonicity are guaranteed.The suggested conditions are those for whichsignals will propagate through the unit withoutsignificant distortion. The absolute conditionsare those for which the unit will produce sometype of output for a given input.

When operating the unit between the

recommended and absolute conditions, thedelays may deviate from their values at low

frequency. However, these deviations will remainconstant from pulse to pulse if the input pulsewidth and period remain fixed. In other words,the delay of the unit exhibits frequency and pulsewidth dependence when operated beyond therecommended conditions. Please consult thetechnical staff at Data Delay Devices if yourapplication has specific high-frequencyrequirements.

Please note that the increment tolerances listedrepresent a design goal. Although most delayincrements will fall within tolerance, they are notguaranteed throughout the address range of theunit. Monotonicity is, however, guaranteed overall addresses.

A2-A0

TAENSEN/

TENISIN

TDAOUT

A i-1TOAXPWINPWOUTDISOTAISAiTDISHFigure 1: Timing Diagram

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PDU138

DEVICE SPECIFICATIONS

TABLE 1: AC CHARACTERISTICS

PARAMETER

Total Programmable DelayInherent Delay

Disable to Output Low DelayAddress to Enable Setup TimeAddress to Input Setup TimeEnable to Input Setup TimeOutput to Address ChangeDisable Hold Time

Absolute

Input PeriodSuggested

RecommendedAbsolute

Input Pulse WidthSuggested

Recommended

SYMBOLTDTTD0TDISOTAENSTAISTENISTOAXTDISHPERINPERINPERINPWINPWINPWIN

MIN

TYP77.012.0

UNITSTINCnsnsnsnsns

2.012.012.0See TextSee Text20502001025100

% of TDT% of TDT% of TDT% of TDT% of TDT% of TDT

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETERDC Supply VoltageInput Pin VoltageStorage TemperatureLead Temperature

SYMBOLVCCVINTSTRGTLEAD

MIN-0.3-0.3-55

MAX7.0VDD+0.3150300

UNITSVVCC

NOTES

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

High Level Output VoltageLow Level Output VoltageHigh Level Output CurrentLow Level Output CurrentHigh Level Input VoltageLow Level Input VoltageInput Clamp Voltage

Input Current at MaximumInput Voltage

High Level Input CurrentLow Level Input CurrentShort-circuit Output CurrentOutput High Fan-outOutput Low Fan-out

SYMBOLVOH

VOLIOHIOLVIHVILVIKIIHHIIHIILIOS

MIN2.5

TYP3.40.35

MAX

UNITSVVmAmAVVVmAµAmAmAUnitLoad

NOTES

VCC = MIN, IOH = MAXVIH = MIN, VIL = MAXVCC = MIN, IOL = MAXVIH = MIN, VIL = MAX

0.5-1.020.0

2.0

0.8-1.20.120-0.6-1502512.5

VCC = MIN, II = IIK

VCC = MAX, VI = 7.0VVCC = MAX, VI = 2.7VVCC = MAX, VI = 0.5VVCC = MAX

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PDU138

PACKAGE DIMENSIONS

1611109.410MAX4578.820 MAX.020TYP.280MAX.150±.030.012 TYP.300TYP.018 TYP.700 TYP.100TYPCommercial DIP (PDU138-xx)

1611109.410MAX4578.820 MAX.020TYP.320MAX.150±.030.012 TYP.300TYP.018 TYP.700 TYP.100TYPMilitary DIP (PDU138-xxM)

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PDU138

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

oo

Ambient Temperature:25C ± 3CSupply Voltage (Vcc):5.0V ± 0.1VInput Pulse:High = 3.0V ± 0.1V

Low = 0.0V ± 0.1V

Source Impedance:50Ω Max.Rise/Fall Time:3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width:PWIN = 1.5 x Total DelayPeriod:PERIN = 4.5 x Total Delay

OUTPUT:

Load:Cload:

Threshold:

1 FAST-TTL Gate5pf ± 10%

1.5V (Rising & Falling)

NOTE:The above conditions are for test only and do not in any way restrict the operation of the device.

COMPUTERSYSTEMPRINTERREFPULSEGENERATOROUTTRIGINDEVICE UNDERTEST (DUT)OUTINTRIGTIME INTERVALCOUNTERTest Setup

PERIN

PWIN

TRISE

INPUTSIGNAL

2.4V1.5V0.6V

TFALL

VIH

2.4V1.5V0.6V

VIL

TDAF

TDAR

OUTPUTSIGNAL

1.5V

VOH

1.5V

VOL

Timing Diagram For Testing

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