UPD70741GC-25-8EU资料

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DATA SHEET

MOS INTEGRATED CIRCUITµPD70741V821TM32-/16-BIT MICROPROCESSORThe µPD70741 (V821) is a 32/16-bit RISC microprocessor that uses, as its processor core, the high-performance 32-bit microprocessor µPD70732 (V810TM) designed for built-in control applications. It incorporatesperipheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serialinterface, and interrupt controller.The V821, which offers quick real-time response, high-speed integer instructions, bit string instructions, andfloating-point instructions, is ideally suited to use in OA equipment such as printers and facsimiles, imageprocessing devices such as those used in navigation units, portable devices, and other devices demandingexcellent cost performance.The functions are described in detail in the following User’s Manuals, which should be read beforestarting design work.•V821 User’s Manual Hardware:U10077E•V810 FamilyTM User’s Manual Architecture:U10082EFEATURESThe V810 32-bit microprocessor is used as the CPU core•Separate address/data busAddress bus:24 bitsData bus:16 bits•Built-in 1-Kbyte instruction cache memory•Pipeline structure of 1-clock pitch•Internal 4-Gbyte linear address space•32-bit general-purpose registers: 32Instructions ideal for various application fields•Floating-point operation instructions and bit stringinstructionsInterrupts controller•Nonmaskable:1 external input•Maskable:8 external inputs and 11 types ofinternal sources•Priorities can be specified in units of four groups.Wait control unit•Capable of CS control over four blocks in both memoryand I/O spaces.•Linear address space of each block: 16M bytesMemory access control functions•Supports DRAM high-speed page mode.•Supports page-ROM page mode.DMA controller (DMAC): 2 channels•Maximum transfer count: 65 536•Two transfer types (fly-by (1-cycle) transfer and2-cycle transfer)•Three transfer modes (single transfer, single-step transfer, and block transfer)Serial interfaces : 2 channels•Asynchronous serial interface (UART):1 channel•Synchronous serial interface (CSI):1 channelReal-time pulse unit•16-bit timer/event counter:1 channel•16-bit interval timerWatchdog timer functionsClock generator functionsStandby functions (HALT, IDLE, and STOP modes):1 channelThe information in this document is subject to change without notice.Document No. U11678EJ4V0DS00 (4th edition)Date Published June 1998 J CP(K)Printed in Japan

The mark shows major revised points.

µPD70741ORDERING INFORMATION

Part number

Package

100-pin plastic LQFP (fine pitch)(14 × 14 × 1.40 mm)

µPD70741GC-25-8EU

PIN CONFIGURATION (TOP VIEW)

100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD70741GC-25-8EU

Caution Connect the IC pin to GND through a resistor.2

GNDIORDIOWRNMIHLDRQHLDAKRXD/P09/TCTXD/P08/UBESCLK/P07SO/P06SI/P05DACK1/P04DREQ1/P03DACK0/P02DREQ0/P01GNDVDDTCLR/P00BLOCK/WDTOUTINTP03INTP02/TO01INTP01INTP00/TO00INTP13/TIVDD123456710111213141516171819202122232425VDDRASUMWRLMWR/WEMRDREADYCS0/REFRQCS1CS2CS3A12A13A14A15A16GNDVDDA17A18A19A20A21A22A23VDD7677787980818283848586878091929394959697991007574737271706968676665636261605958575655535251GNDLCASUCASGNDX1X2VDDCLKOUTVDDGNDA11A10A9A8A7A6GNDVDDA5A4A3A2A1A0VDD5049484744434241403938373635343332313029282726GNDD15D14D13D12D11D10D9D8GNDVDDD7D6D5D4D3D2D1D0ICRESETINTP10INTP11INTP12GNDµPD70741PIN NAMES

A0-A23BLOCKCLKOUTCS0-CS3D0-D15DACK0, DACK1DREQ0, DREQ1HLDAKHLDRQ

INTP00-INTP03, INTP10-INTP13IORDIOWRLCASLMWRMRDNMIP00-P09RASREADYREFRQRESETRXDSCLKSISOTCTCLRTI

TO00, TO01TXDUBEUCASUMWRWDTOUTWEX1, X2

:Address Bus:Bus Lock

:System Clock Out:Chip Select:Data Bus

:DMA Acknowledge:DMA Request:Hold Acknowledge:Hold Request:Interrupt Request:I/O Read:I/O Write

:Lower Column Address Strobe:Lower Memory Write:Memory Read

:Non-maskable Interrupt Request:Port

:Row Address Strobe:Ready

:Refresh Request:Reset:Receive Data:Serial Clock:Serial Input:Serial Output:Terminal Count:Timer Clear:Timer Input:Timer Output:Transmit Data:Upper Byte Enable

:Upper Column Address Strobe:Upper Memory Write:Watchdog Timer Output:Write Enable:Crystal Oscillator

µPD70741INTERNAL BLOCK DIAGRAM

CLKOUTTIV821X1X2RESETCGCPU(V810)ICUUARTWDTOUTWDTCSIHLDAKHLDRQDREQ0, DREQ1DACK0, DACK1TCBAUPORTTO00,TO01RPU4TCLRINTP00-INTP03,INTP10-INTP13TXDRXDSCLKSISOPORT00-PORT09DMACDRAMCBIUROMCWCU/CSNMIA0-A23D0-D15UBERASLCASUCASREFRQWEMRDIORDIOWRLMWRUMWRREADYCS0-CS34

µPD70741CONTENTS

1.PIN FUNCTIONS........................................................................................................................

1.1Port Pins.........................................................................................................................................1.2Non-Port Pins.................................................................................................................................1.3

Pin I/O Circuits and Processing of Unused Pins......................................................................

2.INTERNAL UNITS......................................................................................................................

2.1Bus Interface Unit (BIU)................................................................................................................2.2Wait Control Unit (WCU)...............................................................................................................2.3DRAM Controller (DRAMC)...........................................................................................................2.4ROM Controller (ROMC)................................................................................................................2.5Interrupt Controller........................................................................................................................2.6DMA Controller (DMAC)................................................................................................................2.7Serial Interfaces (UART/CSI)........................................................................................................2.8Real-Time Pulse Unit (RPU).........................................................................................................2.9Watchdog Timer (WDT).................................................................................................................2.10Clock Generator (CG)....................................................................................................................2.11Bus Arbitration Unit (BAU)...........................................................................................................2.12

Port..................................................................................................................................................

3.CPU FUNCTIONS.......................................................................................................................

3.1Features..........................................................................................................................................3.2

Address Space...............................................................................................................................3.2.1Memory map...................................................................................................................3.2.2

I/O map............................................................................................................................3.3

CPU Register Set...........................................................................................................................

3.3.1Program register set.....................................................................................................3.3.2

System register set........................................................................................................

3.4Built-in Peripheral I/O Registers..................................................................................................3.5

Data Types......................................................................................................................................3.5.1Data types.......................................................................................................................3.5.2

Data alignment...............................................................................................................

3.6Cache...............................................................................................................................................

4.INTERRUPT/EXCEPTION HANDLING FUNCTIONS...............................................................

4.1

Features..........................................................................................................................................

5.WAIT CONTROL FUNCTIONS..................................................................................................

5.1

Features..........................................................................................................................................

8810

121212121212121213131313

141415161718192023232526

µPD707416.

MEMORY ACCESS CONTROL FUNCTIONS..........................................................................

6.1

DRAM Controller (DRAMC)...........................................................................................................6.1.1Features..........................................................................................................................6.1.2Address multiplexing function....................................................................................6.1.3Refresh function............................................................................................................6.1.4

Self-refresh function......................................................................................................6.2

ROM Controller (ROMC)................................................................................................................

6.2.1

on-page/off-page decision............................................................................................

7.DMA FUNCTIONS (DMA CONTROLLER)...............................................................................

7.1

Features..........................................................................................................................................

8.SERIAL INTERFACE FUNCTION.............................................................................................

8.1Features..........................................................................................................................................8.2Asynchronous Serial Interface (UART)......................................................................................8.2.1Features..........................................................................................................................8.3Synchronous Serial Interface (CSI).............................................................................................8.3.1Features..........................................................................................................................8.4

Baud Rate Generator (BRG).........................................................................................................

8.4.1

Configuration and function..........................................................................................

9.TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT).................................................

9.1

Features..........................................................................................................................................

10.WATCHDOG TIMER FUNCTIONS............................................................................................

10.1Features..........................................................................................................................................10.2

Operation........................................................................................................................................

11.PORT FUNCTIONS....................................................................................................................

11.1

Features..........................................................................................................................................

12.CLOCK GENERATION FUNCTIONS........................................................................................

12.1

Features..........................................................................................................................................

13.STANDBY FUNCTIONS.............................................................................................................

13.1Features..........................................................................................................................................13.2

Standby Mode................................................................................................................................

14.RESET FUNCTIONS..................................................................................................................

14.1Features..........................................................................................................................................14.2

Pin Functions.................................................................................................................................

15.INSTRUCTION SET....................................................................................................................

15.1Instruction Format.........................................................................................................................15.2

Instruction Mnemonic (In Alphabetical Order)..........................................................................

32323233333333

37373739394040

4344

4747

4949

5052

µPD7074116.ELECTRICAL SPECIFICATIONS..............................................................................................

17.PACKAGE DRAWINGS.............................................................................................................10718.RECOMMENDED SOLDERING CONDITIONS........................................................................108

µPD707411. PIN FUNCTIONS

1.1 Port Pins

Pin nameP00P01P02P03P04P05P06P07P08P09

Input/outputInput/output

Port 0

10-bit input/output portCan be set for input/output bit.

Function

Dual-function pin

TCLRDREQ0DACK0DREQ1DACK1SISOSCLKTXD/UBERXD/TC

Remark After a reset is released, each port pin is set as an input port pin.1.2 Non-Port Pins

(1/2)

Pin nameA0-A23D0-D15READYHLDRQHLDAKBLOCKMRDLMWRUMWRIORDIOWRUBERESETX1, X2

Input/outputTristate outputTristate input/outputInputInputOutputOutputTristate outputTristate outputTristate outputTristate outputTristate outputTristate outputInputInput

Address bus signal

Bidirectional data bus signalBus cycle termination permit signalBus mastership request signalBus mastership permit signalBus mastership prohibit signalRead strobe signal to memory

Write strobe signal to lower data in memoryWrite strobe signal to upper data in memoryRead strobe signal to I/O dataWrite strobe signal to I/O dataData bus upper data enable signalSystem reset input

Crystal connection/external clock input

---TXD/P08

--Function

Dual-function pin

-----WDTOUT

µPD70741(2/2)

Pin nameCLKOUTCS0CS1CS2CS3INTP00INTP01INTP02INTP03INTP10INTP11INTP12INTP13NMIREFRQRASLCASUCASWEDREQ0DREQ1DACK0DACK1TCTO00TO01TCLRTITXDRXDSCLKSOSIWDTOUTICVDDGND

InputInputOutputInputInput/outputOutputInputOutput

---External clear or start signal input to timer 0External count clock input to timer 0UART serial data outputUART serial data inputCSI serial clock input/outputCSI serial data outputCSI serial data inputWDT overflow signal

Internal connection (must be connected to GND through a resistor)Supplies positive power.Ground potential

Input

Tristate outputTristate outputTristate outputTristate outputTristate outputInputInputOutputOutputOutputOutput

Nonmaskable interrupt request inputRefresh request signal to DRAMRow address strobe signal to DRAM

Column address strobe signal to lower data in DRAMColumn address strobe signal to upper data in DRAMWrite strobe signal to DRAMDMA request signal (channel 0)DMA request signal (channel 1)DMA permit signal (channel 0)DMA permit signal (channel 1)DMA end signalRPU pulse output

LMWRP01P03P02P04RXD/P09INTP00INTP02P00INTP13UBE/P08TC/P09P07P06P05BLOCK

---CS0

---TI

-TO01

----Input

Interrupt request input

TO00

-Input/outputOutputTristate output

System clock outputChip select signal

REFRQ

---Function

Dual-function pin

µPD707411.3 Pin I/O Circuits and Processing of Unused Pins

Table 1-1 shows the I/O circuit type of each pin and the processing for unused pins. Figure 1-1 shows the I/Ocircuit of each type.

Table 1-1. I/O Circuits Type of Each Pin and Recommended Connection of Unused Pins

P00/TCLRP01/DREQ0P02/DACK0P03/DREQ1P04/DACK1P05/SIP06/SOP07/SCLKP08/TXD/UBEP09/RXD/TCD0-D15A0-A7, A16-A18A8-A15, A19-A23READYHLDRQHLDAK

BLOCK/WDTOUTMRDLMWR/WEUMWRIORDIOWRCLKOUTCS0/REFRQCS1-CS3INTP00/TO00INTP01INTP02/TO01INTP03INTP10-INTP12INTP13/TINMIRESETRASLCASUCASX2IC

--Connected to GND through a resistor.

Open

8282

Connected to VDD through a resistor.Connected to VDD through a resistor.Connected to VDD through a resistor.Connected to VDD through a resistor.

441

Open

Connected to GND through a resistor.Connected to VDD through a resistor.Open

Open

I/O circuit type

Input status:

Recommended connection

Individually connected to VDD or GND through a resistor.

Output status: Open

µPD70741Figure 1-1. Pin I/O Circuits

Type 1VDDType 5VDDDataOutputdisableP-chN-chIN/OUTINP-chN-chInputenableType 2Type 8VDDDataINP-chIN/OUTOutputdisableN-chSchmitt trigger input with hysteresis characteristicsType 4VDDDataP-chOUTOutputdisableN-chPush-pull output which can output high impedance (Both the positive and negative channels are off.)11

µPD707412. INTERNAL UNITS

2.1 Bus Interface Unit (BIU)

Controls the pins of the address bus, data bus, and control bus. A bus cycle activated by the CPU or DMAC iscontrolled via the WCU, DRAMC, and ROMC.2.2 Wait Control Unit (WCU)

Manages the four blocks corresponding to four chip select signals (CS0-CS3).

This block generates chip select signals, performs wait control, and selects a bus cycle type.2.3 DRAM Controller (DRAMC)

Generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to DRAM.

This block supports DRAM high-speed page mode. Access to DRAM can be of either of two types, each havinga different cycle, normal access (off-page) or high-speed page access (on-page).2.4 ROM Controller (ROMC)

Supports access to ROM supporting a page access function.

Performs address comparison relative to the previous bus cycle and performs wait control for normal access (off-page)/page access (on-page). It supports page widths of 8- bytes.2.5 Interrupt Controller

Handles maskable interrupt requests (INTP00-INTP03, INTP10-INTP13) from both the built-in and externalperipheral hardware. Priorities can be specified for these interrupt requests, in units of four groups. It can applymultiple handling control to the interrupt sources.2.6 DMA Controller (DMAC)

Transfers data between memory and I/O, as instructed by the CPU.

There are two address modes, fly-by (1-cycle) transfer and 2-cycle transfer. There are three bus modes, singletransfer, single-step transfer, and block transfer.2.7 Serial Interfaces (UART/CSI)

As serial interfaces, the V821 features an asynchronous serial interface (UART) and a synchronous serial interface(CSI), one channel being assigned to each.The UART transfers data via pins TXD and RXD.The CSI transfers data via pins SO, SI, and SCLK.

Either the baud rate generator or the system clock can be selected as the serial clock source.2.8 Real-Time Pulse Unit (RPU)

This block incorporates a 16-bit timer/event counter and a 16-bit interval timer. It can calculate pulse intervalsand frequencies and output programmable pulses.

µPD707412.9 Watchdog Timer (WDT)

This block incorporates an 8-bit watchdog timer to detect a program hanging up or system errors. If the watchdogtimer overflows, the WDTOUT pin becomes active.2.10 Clock Generator (CG)

Supplies clock pulses at a frequency five times greater than that of the oscillator connected to pins X1 and X2 (whenthe built-in PLL is being used) or at half the frequency (when the built-in PLL is not being used) of the operating clockpulses for the CPU. Also, instead of connecting an oscillator, external clock pulses can be input.2.11 Bus Arbitration Unit (BAU)

Arbitrates any contention over bus mastership between the bus masters (CPU, DRAMC, DMAC, external busmaster). Bus mastership can be switched in each bus cycle and also in the idle state.2.12 Port

Port 0 provides a total of ten input/output port pins. The pins can be used as either port or control pins.

µPD707413. CPU FUNCTIONS

The CPU has functions equivalent to those of the V810 microprocessor, designed for built-in control. It offers bitstring instructions, floating-point instructions, and quick real-time response.3.1 Features

The features of the CPU are:

•High-performance 32-bit RISC microprocessor

•Built-in 1-Kbyte cache memory•Pipeline structure of 1-clock pitch•16-bit data bus

•32-bit general-purpose registers: 32•4-Gbyte linear address space

•Instructions ideal for various application fields

•Floating-point operation instructions (conforming to the IEEE7 data format)•Bit string instructions

•High-speed interrupt response•Debug support functions

3.2 Address Space

The V821 supports internal memory and I/O spaces of 4G bytes each. The V821 outputs 24-bit addresses tomemory and I/O, such that the addresses range from 0 to 224 - 1.

In byte data, bit 0 is defined as the LSB (Least Significant Bit) and bit 7 as the MSB (Most Significant Bit). In multiple-byte data, bit 0 of the byte data in the lower address is defined as the LSB and bit 7 of the byte data in the upperaddress as the MSB, unless noted otherwise.

In the case of the V821, 2-byte data is referred to as halfword data, and 4-byte data as word data. In this datasheet, in representations of multiple-byte memory and I/O data, the right address corresponds to the lower addressand the left address to the upper address, as shown below.

Byte of address A7A (address)0Halfword of address A15870A + 131A + 32423A + 21615A + 1A (address)87A (address)0Word of address A/short real14

µPD707413.2.1 Memory map

Figure 3-1 shows the memory map of the V821.

The internal 4-Gbyte memory space is divided into blocks of 1G byte each.

Each block has a linear address space of 16M bytes. (The lower 24 bits of a 32-bit address are output.)

Figure 3-1. Memory Map

FFFFFFFFHInterrupt handler tableNote

FFFFFE00HFFFFFDFFHBlock 3C0000000HBFFFFFFFHBlock 280000000H7FFFFFFFHBlock 140000000H3FFFFFFFHBlock 000000000HNote See Table 4-1 for details.15

µPD707413.2.2 I/O map

Figure 3-2 shows the I/O map of the V821.

The internal 4-Gbyte memory space is divided into blocks of 1G byte each.

Each block has a linear address space of 16M bytes. (The lower 24 bits of a 32-bit address are output.)The V821 reserves I/O addresses C0000000H-FFFFFFFFH (I/O block 3) as an internal I/O space. Each unit ismapped to this internal I/O space.

See Section 3.4 for details of the configuration of the internal I/O space.

Figure 3-2. I/O Map

FFFFFFFFHBlock 3 (Internal I/O)C0000000HBFFFFFFFHBlock 280000000H7FFFFFFFHBlock 140000000H3FFFFFFFHBlock 000000000H16

µPD707413.3 CPU Register Set

The registers of the V821 belong to one of two sets, the general-purpose program register set and the dedicatedsystem register set. All registers are 32 bits in wide.

Program register set310r0Zero Registerr1Reserved for Address Generationr2Handler Stack Pointer (hp)r3Stack Pointer (sp)r4Global Pointer (gp)r5Text Pointer (tp)r6r7r8r9r10r11r12r13r14r15r16r17r18r19r20r21r22r23r24r25r26String Destination Bit Offsetr27String Source Bit Offsetr28String Lengthr29String Destinationr30String Sourcer31Link Pointer (lp)310PCProgram CounterSystem register set310EIPCException/Interrupt PCEIPSWException/Interrupt PSW310FEPCFatal Error PCFEPSWFatal Error PSW310ECRException Cause Register310PSWProgram Status Word310PIRProcessor ID Register310TKCWTask Control Word310CHCWCache Control Word310ADTREAddress Trap Register17

µPD707413.3.1 Program register set

The program register set includes general-purpose registers and a program counter.(1)General-purpose registers

The V821 has 32 general-purpose registers, r0-r31. These registers can be used for data or address variables.Registers r0 and r26-r30 are used implicitly with instructions. Caution is therefore necessary when using theseregisters. Registers r1-r5 and r31 are used implicitly by the assembler and the C compiler. Before using theseregisters, therefore, the contents of the registers must be saved to prevent their being destroyed. After usingthe registers, their contents must be restored.

Table 3-1. Program Registers

Namer0r1r2r3r4r5r6-r25r26r27r28r29r30r31

Zero register

Assembler-reserved registerHandler stack pointerStack pointerGlobal pointerText pointer

-String destination start bit offsetString source start bit offsetString length register

String destination start address registerString start address registerLink pointer

Stores a return point address according to the execution of a JAL instruction.Use

Always stores zeros.

Used as a working register to create 32-bit immediate.Used as a stack pointer for the handler.Used to create a stack frame at a function call.Used to access a global variable in a data area.Points to the top of a text areaRegister for an address/data variableUsed to execute a bit string instruction.

Explanation

(2)Program counter

Stores the address of an instruction while a program is running. Bit 0 of the program counter (PC) is fixed to0, thus preventing a branch to an odd address. It is initialized to FFFFFFF0H at reset.

µPD707413.3.2 System register set

System registers are used to control the state of the CPU and store interrupt information.

Table 3-2. System Register Numbers

No.0

Use

Registers for saving the currentstatus upon the occurrence of anexception or interrupt

Explanation

Retain the contents of PC and PSW if an exception orinterrupt occurs. Note, however, that there is only onepair of these registers.

When multiple interrupts are allowed, therefore, the

contents of the registers must be saved by the program.Retain the contents of PC and PSW if anNMI or double exception occurs.

Stores the source of an exception, maskable interrupt, orNMI. The upper 16 bits of this register are called

\"FECC\" and set to the exception code of an NMI/doubleexception. The lower 16 bits are called \"EICC\" and setto the exception code of an exception/interrupt.The program status word is a set of flags indicating thestate of the program (result of executing an instruction)and the state of the CPU.

Used to identify a CPU type number.Used to control a floating-point operation.

1234

EIPSWFEPCFEPSWECR

Registers for saving the currentstatus upon the occurrence of anNMI or double exceptionException source register

5PSWProgram status word

678-23242526-31

PIRTKCWReservedCHCWADTREReserved

Processor ID registerTask control word

Cache control wordAddress trap register

Used to control the built-in instruction cache.

Stores the address used to detect an address match withPC, and to generate an address trap.

Read and write operations made to these system registers can be performed using the system register load/storeinstructions (LDSR and STSR) with the system register numbers specified.

µPD707413.4 Built-in Peripheral I/O Registers

The built-in peripheral I/O registers are allocated to the 256-byte area between C0000000H and C00000FFH inthe 1-Gbyte space between C0000000H and FFFFFFFFH. Starting from address C0000100H, 256-byte images arecreated every 256 bytes.

The least significant bit of an address is not decoded. Thus, when byte access is attempted to a register at anodd address (2n+1), a register at an even address (2n) is actually performed.

When 16-bit access is attempted to an 8-bit I/O register, the upper eight bits are ignored for write, and becomeundefined for read.

Table 3-3 lists the built-in peripheral I/O registers.

µPD70741Table 3-3. Built-in Peripheral I/O Registers (1/2)

Manipulatable bits8-bits

C0000010C0000012C0000014C0000020C0000022C0000024C0000026C0000028C000002AC000002CC0000040C0000042C0000044C0000046C0000048C000004AC000004CC000004EC0000050C0000052C00000C0000056C0000060C0000062C00000C0000066C0000068C0000070C0000072C0000074C0000076C0000078C000007CC000007EC0000080C0000082

Port mode control register 0Port mode register 0Port register 0

Bus cycle type control registerProgrammable wait control register 0Programmable wait control register 1Programmable wait control register 2DRAM configuration registerRefresh control register

Page-ROM configuration registerDMA source address register 0HDMA source address register 0LDMA destination address register 0HDMA destination address register 0LDMA source address register 1HDMA source address register 1LDMA destination address register 1HDMA destination address register 1LDMA byte count register 0DMA byte count register 1DMA channel control register 0DMA channel control register 1Timer unit mode register 0Timer control register 0Timer control register 1Timer output control register 0Timer overflow status registerTimer register 0

Capture/compare register 00Capture/compare register 01Capture/compare register 02Capture/compare register 03Timer register 1Compare register 1

PMC0PM0P0BCTCPWC0PWC1PWC2DRCRFCPRCDSA0HDSA0LDDA0HDDA0LDSA1HDSA1LDDA1HDDA1LDBC0DBC1DCHC0DCHC1TUM0TMC0TMC1TOC0TOVSTM0CC00CC01CC02CC03TM1CM1

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0000H03FFHNot defined01H77H77H77H81H80H80HNot definedNot definedNot definedNot definedNot definedNot definedNot definedNot definedNot definedNot defined0000H0000H0A00H00H00H03H00H0000HNot definedNot definedNot definedNot defined0000HNot defined00H00H

AddressFunction register nameAbbreviationInitial value

Asynchronous serial interface mode registerASIMAsynchronous serial interface status registerASIS

µPD70741Table 3-3. Built-in Peripheral I/O Registers (2/2)

Manipulatable bits8-bits

C0000084C0000086C0000088C000008AC0000090C0000092C00000A0C00000A2C00000B0C00000B2C00000B4C00000B6C00000B8C00000C0C00000D0C00000E0

Reception bufferReception buffer LTransmission shift registerTransmission shift register L

Synchronous serial interface mode registerSerial I/O shift registerBaud rate generator register

RXBRXBLTXSTXSLCSIMSIOBRG

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Not definedNot definedNot definedNot defined00HNot definedNot defined00HE4H0000H0000HFFFFHAAAAH00H00H03H

AddressFunction register nameAbbreviationInitial value

Baud rate generator prescale mode registerBPRMInterrupt group priority registerInterrupt clear registerInterrupt request registerInterrupt request mask registerICU mode registerWDT mode registerStandby control registerClock control register

IGPICRIRRIMRIMODWDTMSTBCCGC

µPD707413.5 Data Types3.5.1 Data types

The data types supported by the V821 are as follows: •Integer (8, 16, 32 bits)

•Unsigned integer (8, 16, 32 bits) •Bit string

•Single-precision floating-point data (32 bits)(1) Data type and addressing

The V821 uses the little-endian data addressing. In this addressing, if fixed-length data is located in a memoryarea, the data must be either of the data types shown below.(a)Byte

A byte is consecutive 8-bit data whose first-bit address is aligned to a byte boundary. Each bit in a byte isnumbered from 0 to 7: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 7. Toaccess a byte, specify address A. (See diagram below.)

70A(b)Halfword

A halfword is consecutive 16-bit (= 2 bytes) data whose first-bit address is aligned to a halfword boundary.Each bit in a halfword is numbered from 0 to 15: LSB (the least significant bit) is bit 0 and MSB (the mostsignificant bit) is bit 15. To access a halfword, specify the address A only (lowest bit must be 0).

15870A + 1A(c)Word/short real

A word, also called short real, is consecutive 32-bit (= 4 bytes) data whose first-bit address is aligned to aword boundary. Each bit in a word is numbered from 0 to 31: LSB (the least significant bit) is bit 0 and MSB(the most significant bit) is bit 31. To access a word or short real, specify the address A only (lower two bitsmust be 0).

3124231615870A + 3A + 2A + 1A23

µPD70741(2)Integer

In the V821, all integers are expressed in the two’s-complement binary notation, and are composed of either 8bits, 16 bits, or 32 bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered bitsexpress higher digits of the integer with the highest bit expressing its sign.

Data lengthByte

HalfwordWord

8 bits16 bits32 bits

Range

-128 to +127-32 768 to +32 767

-2 147 483 8 to +2 147 483 7

(3)Unsigned integer

An unsigned integer is either zero or a positive integer unlike the integer explained in (2) which can be negativeas well as zero and positive. Unsigned integers are expressed in the binary notation in the same way as integers,and are either 8 bits, 16 bits, or 32 bits long. Regardless of the data length, the bit assignments are the sameas in the case of integers except that unsigned integers do not include a sign bit; the highest bit is also a partof the integer.

Data lengthByte

HalfwordWord

8 bits16 bits32 bits

Range

0 to 2550 to 65 535

0 to 4 294 967 295

(4)Bit string

A bit string is a type of data whose bit length is variable from 0 to 232 - 1. To specify a bit-string data, definethe following three attributes.

•A:address of the string data’s first word (lower two bits must be 0.) •B:in-word bit offset in the string data (0 to 31) •M:bit length of the string data (0 to 232 - 1)

The above three attributes may vary depending on the bit-string data manipulation direction: upward or downward,as shown below. The former is the direction from lower addresses to higher addresses while the latter is the directionfrom higher to lower addresses.

µPD70741M - 1M0A + 8DA + 4A (Word boundary)BAttributeFirst-word address (0s in bits 1 and 0)In-word bit offset (0 to 31)32Bit length (0 to 2 - 1)UpwardABMDownwardA + 4DM(5) Single-precision floating-point data

This data type is 32 bits long and its bit allocation complies with the IEEE single format. A single-precision floating-point data consists of 1-bit mantissa sign bit, 8-bit exponent, and 23-bit mantissa. The exponent is offset-expressed from the bias value - 127, and the mantissa is binary-expressed with the integer part omitted.

3130sexp (8)2322mantissa (23)03.5.2 Data alignment

In the V821, a word data must be aligned to a word boundary (with the lowest two bits of the address fixed to 0s),and a halfword data to a halfword boundary (with the lowest bit of the address fixed to 0). If a data is not alignedas specified, the lowest two bits (in the case of word) or one bit (in the case of halfword) of its address will forciblybe masked with 0s when the data is accessed.

µPD707413.6 Cache

Figure 3-3 shows the instruction cache configuration provided to the V821.

Figure 3-3. Cache Configuration

: 1 KbytesCapacity Mapping system: direct map: 8 bytesBlock sizeSub-block size: 4 bytes31Memory addressTAG109Index32Offset0Tag memory(ICHT27 to ICHT0)27Entry 0Entry 12221TAG31 to TAG10031Data memory(ICHD31 to ICHD0)0Sub-block (4 bytes)Block(8 bytes)128 entries128 blocksEntry 127Valid bits (1 bit for every 4 bytes)NECRV (Reserved by NEC)26

µPD707414. INTERRUPT/EXCEPTION HANDLING FUNCTIONS

The V821 features an interrupt controller (ICU) that is dedicated to interrupt handling. The V821 thus supportsa powerful interrupt handling function capable of handling interrupt requests issued by up to 16 sources.

As referred to in this manual, an interrupt is an event which occurs independently of program execution while anexception is an event that depends on program execution. In general, an exception assumes a higher priority thanan interrupt.

The V821 can handle interrupt requests issued by both built-in peripheral hardware and external devices.Exception handling can be triggered by executing an instruction (TRAP instruction) as well as by the occurrence ofan exception (such as an address trap or invalid instruction code).4.1 Features

Interrupts

•Nonmaskable interrupt:1 source•Maskable interrupt

:15 sources

•Programmable priority control with four groups•Multiple interrupt handling control according to priority•Mask specification for each maskable interrupt request•Valid edge specification for external interrupt requests

•The noise eliminator introducing an analog delay (60 to 300 ns) is incorporated into the nonmaskableinterrupt (NMI) pin.Exceptions

•Software exception: 32 sources•Exception trap

: 10 sources

Table 4-1 lists the interrupt and exception sources.

µPD70741Table 4-1. Interrupts (1/2)

Type

Category

GroupPriority

in group

Reset

Interrupt

--------------------------NameRESETNMITRAP1nHTRAP0nHDP-EXAD-TRI-OPCDIV0FIZFZDFOVFUDFPR

Interrupt/exception source

SourceReset inputNMI inputtrap instructiontrap instructionDouble exceptionAddress trapInvalid instructioncode

Division by zeroInvalid floating-point operationFloating-pointdivision by zeroFloating-pointoverflowFloating-pointunderflowNote 4Floating-pointdegraded

precisionNote 4Floating-pointreserved operand

Unit-------------ExceptioncodeFFF0HFFD0HFFBnHFFAnH

Note 3

HandleraddressFFFFFFF0HFFFFFFD0HFFFFFFB0HFFFFFFA0HFFFFFFD0HFFFFFFC0HFFFFFF90HFFFFFF80HFFFFFF60HFFFFFF60HFFFFFF60HFFFFFF60HFFFFFF60H

ReturnPCNote 1UndefinedNextPCNote 2Next PCNext PCCurrentPC

Non-Interrupt

maskableSoftwareexception

ExceptionExceptiontrap

Exception

FFC0HFF90HFF80HFF70HFF68HFFHFF62HFF61H

--FRO-FF60HFFFFFF60H

Remarkn = 0H to FH

Notes1.PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling

2.Return PC = current PC if an interrupt occurred during the execution of an instruction which was stoppedby an interrupt (DIV/DIVU, floating-point, and bit string instructions).

3.The exception code for the exception which occurred first is written into in the 16 low-order bits of ECR,while and that for the second exception is written into the 16 high-order bits.

4.The V821 is not subject to floating-point underflow or degraded precision exceptions.

µPD70741Table 4-1. Interrupts (2/2)

Type

CategoryGroup

Priorityin group

MaskableInterrupt

GR3

3210

GR2

321

NameRESERVEDINTOV0INTSERINTP13INTSRINTSTINTCSI

Interrupt/exception source

SourceReservedTimer 0overflowUART recep-tion errorINTP13 pininputUART recep-tion endUART trans-mission endCSI transmis-sion/receptionendINTP12 pininputDMA transferendINTP00 pininput/CC00matchINTP01 pininput/CC01matchINTP11 pininputCM1 matchINTP02 pininput/CC02matchINTP03 pininput/CC03matchINTP10 pininput

Unit-RPUUARTExternalUARTUARTCSI

ExceptioncodeFEF0HFEE0HFED0HFEC0HFEB0HFEA0HFE90H

HandleraddressFFFFFEF0HFFFFFEE0HFFFFFED0HFFFFFEC0HFFFFFEB0HFFFFFEA0HFFFFFE90H

ReturnPCNote 1NextPCNote 2

GR1

INTP12INTDMAINTP00/INTCC00INTP01/INTCC01INTP11INTCM1INTP02/INTCC02INTP03/INTCC03INTP10

ExternalDMACExternal/RPUExternal/RPUExternalRPUExternal/RPUExternal/RPUExternal

FE80HFE70HFE60H

FFFFFE80HFFFFFE70HFFFFFE60H

1FE50HFFFFFE50H

GR0

FE40HFE30HFE20H

FFFFFE40HFFFFFE30HFFFFFE20H

1FE10HFFFFFE10H

0FE00HFFFFFE00H

Notes1.PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling

2.Return PC = current PC if an interrupt occurred during the execution of an instruction which was stoppedby an interrupt (DIV/DIVU, floating-point, and bit string instructions).

CautionThe exception code and handler address for a maskable interrupt assume the values existing

when the default priority is specified.

µPD707415. WAIT CONTROL FUNCTIONS

The wait control unit (WCU) manages the four blocks corresponding to the four chip select signals, generates thechip select signals, performs wait control, and selects the bus cycle types.5.1 Features

•Able to control up to four blocks in the memory and I/O spaces•Linear address space of each block: 16 Mbytes•Wait control

•Automatic insertion of 0-7 waits per block•Insertion of waits using the READY pin

•Bus cycle selection function

•Page-ROM cycle selectable (address block 3)•DRAM cycle selectable (address block 0)

Figure 5-1. Memory and I/O Maps

(1) Memory map(2) I/O mapFFFFFFFFHBlock 3 (1 Gbyte) C0000000HBFFFFFFFHBlock 2 (1 Gbyte)80000000H7FFFFFFFHBlock 1 (1 Gbyte)40000000H3FFFFFFFHBlock 0 (1 Gbyte) 00000000H16 MbytesImage Image FFFFFFFFHC0000000HBFFFFFFFHBlock 3 (1 Gbyte) Internal I/OBlock 2 (1 Gbyte)Image 16 MbytesImage Image 80000000H7FFFFFFFHBlock 1 (1 Gbyte)40000000H3FFFFFFFHBlock 0 (1 Gbyte)16 Mbytes ImageImageImage 00000000HImage30

µPD70741Table 5-1. Bus Cycles during Which the Wait Function Is Effective

Bus cycle

SRAM (ROM) cycle (Blocks 0-3)DRAM cycle (Block 0)

off-pageon-page

Page-ROM cycle (Block 3)

off-pageon-page

External I/O cycle (Blocks 0-2)Internal I/O cycle (Block 3)CBR refresh cycleCBR self-refresh cycleFly-by DMA transfer

SRAM (ROM) cycle (Blocks 0-3)DRAM cycle (Block 0)

off-pageon-page

Page-ROM cycle (Block 3)

off-pageon-page

Halt acknowledge cycle

Machine fault cycle (I/O block 0 write)

0-7 waits2-7 waits0-7 waits0-7 waits0-7 waitsFixed (0 wait)0-7 wait

oo××××o

Programmable wait0-7 waits2 or 3 waits0 or 1 wait0-7 waits0 or 1 wait0-7 waits1 or 2 waitsFixed (3 waits)-oo×××o×o×

Wait with the READY pin

Remarko: Effective

×: Not effective

µPD707416. MEMORY ACCESS CONTROL FUNCTIONS

6.1 DRAM Controller (DRAMC)

The DRAM controller (DRAMC) generates the REFRQ, RAS, LCAS, and UCAS signals, and controls access toDRAM. Access to DRAM is achieved by multiplexing the DRAM row and column addresses and outputting them fromthe address pins.

The microprocessor assumes the connected DRAM to be of × 4 bits or more, and that it supports high-speed pagemode. There are two types of DRAM access cycles, on-page (2 or 3 clock pulses) and off-page (4 or 5 pulses).Refresh uses the CAS before RAS method, allowing the user to set any refresh period. In IDLE and STOP modes,CBR self-refresh is performed.6.1.1 Features

••••

Generates the REFRQ, RAS, LCAS, and UCAS signals.Supports DRAM high-speed page mode.

Address multiplexing function: 8, 9, 10, and 11 bitsCBR refresh and CBR self-refresh functions

6.1.2 Address multiplexing function

In the DRAM cycle, row and column addresses are multiplexed according to the value of the DAW bits of the DRAMconfiguration register (DRC), then output, as shown in Figure 6-1. In Figure 6-1, a0-a23 are the addresses outputfrom the CPU, while A0-A23 are the address pins of the V821. For example, if DAW = 11, row address a12-a22 andcolumn address a1-a11 are output from address pins (A1-A11).

Table 6-1 lists the relationship between the connectable DRAMs and address multiplexing widths. Depending onthe connected DRAM, the DRAM space can be between 128 Kbytes and 8 Mbytes.

Figure 6-1. Output of Row and Column Addresses

Address pinRow addressDAW = 11DAW = 10DAW = 01DAW = 00Column addressA23A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0a23a23a23a23a23a16a16a16a16a15a14a13a23a22a21a20a15a14a23a22a21a20a19a15a23a22a21a20a19a18a23a22a21a20a19a18a17a19a18a17a16a15a14a13a12a11a18a17a16a15a14a13a12a11a10a17a16a15a14a13a12a11a10a16a15a14a13a12a11a10a9a9a8a032

µPD70741Table 6-1. Examples of DRAM and Address Multiplexing Width

Address multiplexing widthDRAM capacity (in bits) and configuration256 K

8 bits9 bits

K × 4

--10 bits

--11 bits

-1 M-256 K × 4

----4 M-256 K × 16512 K ×81 M ×4

--16 M---1M× 162M×84 M ×4

128 K512 K1M2 M4M8M

DRAM space (in bytes)

6.1.3 Refresh function

DRAMC can automatically generate the distributed CBR refresh cycle needed to refresh external DRAM. Whetherrefresh should be enabled or disabled, and the refresh interval, are specified using the refresh control register (RFC).While another bus master is occupying a bus, DRAMC cannot forcibly acquire the bus. In this case, in responseto a refresh request issued from DRAMC, BAU makes the HLDAK pin inactive to post notification of the occurrenceof a refresh request. In this state, by making the HLDRQ pin inactive, the refresh cycle is activated.6.1.4 Self-refresh function

DRAMC generates the CBR self-refresh cycle in IDLE and STOP modes. The self-refresh cycle is activated bysetting the SMD bit of the standby control register (STBC) to IDLE or STOP mode and executing the HALT instruction.To enable DRAM to perform self-refresh, the standard RAS pulse width for DRAM (100 µs or greater) must beensured.

Self-refresh is canceled using the RESET or NMI pin. The procedure for cancellation by RESET input is the same

as that for normal reset.

6.2 ROM Controller (ROMC)

The ROM controller supports access to ROM having a page access function (page-ROM).

The ROM controller performs address comparison with the previous bus cycle and performs wait control for normalaccess (off-page)/page access (on-page). It supports page widths of 8- bytes.The page-ROM cycle is supported with address block 3.6.2.1 on-page/off-page decision

Whether the page-ROM cycle is on-page or off-page is determined by latching the address during the previouscycle and comparing it with the address during the current cycle.

The address(es) (A3-A5) to be masked (not compared) is set using the page-ROM configuration register (PRC),according to the configuration of the connected page-ROM and the number of consecutively readable bits.

µPD70741Figure 6-2. on-page/off-page Decision When ROM Having a Page Access Function Is Connected

(1) For 16-Mbit ROM (1-Mbit × 16)Internal address latchSetting of thePRC registerV821 outputaddressmrqa31a30(Same address block)Memory access Comparison Compa-rison a23a22a21a20a19a18a5a4a3MA5MA4MA3000Compa-rison Comparison on/off-pageA2A1A0MRQa31a30(Internal) A23A22A21A20A19A18A5A4A3A'19A'18A'17A'4A'3A'2A'1A'0In-page addressConsecutively readable bits: 16 bits × 4 (2) For 16-Mbit ROM (2-Mbit × 8)Internal address latchSetting of thePRC registerV821 outputaddressmrqa31a30(Same address block)Memory access Comparison Compa-rison a23a22a21a20a19a18a5a4a3MA5MA4MA3100Compa-rison Comparison ×on/off-pageA2A1A0MRQa31a30(Internal)A23A22A21A20A19A18A5A4A3A'19A'18A'17A'4A'3A'2A'1A'0A'-1In-page addressConsecutively readable bits: 8 bits × 834

µPD707417. DMA FUNCTIONS (DMA CONTROLLER)

The V821 includes a DMA (Direct Memory Access) controller that executes and controls DMA transfer.The DMAC (DMA controller) transfers data between memory and I/O, or within memory, based on DMA requestsissued by the built-in peripheral hardware (serial interfaces and timer), external DREQ pins, or software triggers.7.1 Features

•Two independent DMA channels•Transfer units: 8/16 bits

•Maximum transfer count: 65 536 (216)•

Two types of transfer• Fly-by (one-cycle) transfer• Two-cycle transfer

•Three transfer modes

• Single transfer mode• Single-step transfer mode• Block transfer mode

•Transfer requests

• External DREQ pin (× 2)

• Requests from built-in peripheral hardware (serial interfaces and timer)• Requests from software

•Transfer objects

• Memory to I/O and vice versa• Memory to memory and vice versa

•Programmable wait function

•DMA transfer end output signal (TC)

µPD70741Figure 7-1. Block Diagram of DMAC

I/OBus interfaceROMExternal data busPeripheral data busAddress control sectionDMA source address registersRAMData control sectionInternal data busDMA destination address registersI/OCount control sectionDMA byte count registersI/OChannel control sectionDMA channel control registers INTDMAINTCM1INTSRINTSTINTCSITCDREQ36

DACKµPD707418. SERIAL INTERFACE FUNCTION

8.1 Features

The V821 provides two transmission and reception channels as part of its serial interface function.

The two interface modes listed below are supported, one channel being provided for each mode. The two modesoperate independently of each other.(1)Asynchronous serial interface (UART)(2)Synchronous serial interface (CSI)

In UART mode, one-byte serial data is transmitted or received after a start bit, and full-duplex communication isenabled.

In CSI mode, data is transferred using three signal lines (three-wire serial I/O): the serial clock (SCLK), serial input(SI), and serial output (SO).

8.2 Asynchronous Serial Interface (UART)8.2.1 Features

Transfer rate110 bps to 38 400 bps(when BRG is used with φ = 25 MHz)

781 Kbps maximum

Full-duplex communication

Two-pin configurationTXD:Transmission data output pin

RXD:Reception data input pin

Reception error detection function•Parity error•Framing error•Overrun error

Interrupt source (3 types)

•Reception error interrupt (INTSER)•Reception completion interrupt (INTSR)•Transmission completion interrupt (INTST)

The character length for transmission and reception data is specified upon ASIM reception.Character length:7 or 8 bits

9 bits (when an extended bit is used)

Parity function: Odd parity, even parity, zero parity, without parityTransmission stop bit: 1 or 2 bitsOn-chip baud rate generator

(when φ/2 is used with φ = 25 MHz)

µPD70741Figure 8-1. Block Diagram of Asynchronous Serial Interface

Internal bus16/8816/8ReceptionRXBbufferRXBL8ASISRXDTXDReception control parity checkReception shift register PEFEOVESOTASIMSLSCLSRXEPSEBSCLTransmission TXSshift register TXSLINTSRTransmission INTSERcontrol parity bit additionINTST12Selector116116φBaud rate generator 38

µPD707418.3 Synchronous Serial Interface (CSI)8.3.1 Features

High-speed transfer 6.25 Mbps maximum (when φ/2 is used with φ = 25 MHz)Half-duplex communicationCharacter length: 8 bits

Switchable between the MSB and LSB to lead data transfer

Allows selection between external serial clock input and internal serial clock outputThree-wire method

SOSI

One interrupt source

• Interrupt request signal (INTCSI)

Figure 8-2. Block Diagram of Clock Synchronous Serial Interface

:Serial data output:Serial data input

SCLK:Serial clock I/O pin

Internal busCSIMCTXECRXESOTMODCLSSO latchSIShift register (SIO)DQSOSCLKSerial clock control circuitSelector12Serial clock counterInterrupt control circuitSelectorBaud rate generatorφ/2φINTCSI39

µPD707418.4 Baud Rate Generator (BRG)8.4.1 Configuration and function

With the serial interface, a serial clock chosen from the baud rate generator output and clocks generated usingthe system clock (φ) can be used as a baud rate.

A serial clock source can be specified by using the SCLS bit of the ASIM register when the UART is used, or byusing the CLS bit of the CSIM register when the CSI is used.

When baud rate generator output is specified, the baud rate generator is selected as the clock source.The same serial clock is used for both transmission and reception on a channel, so that the same baud rate appliesto transmission and reception.

Figure 8-3. Block Diagram

Internal bus7BRG0BPRMBRCEBPRMatchUARTClearCSI12TMBRGPrescalerφφ/240

µPD707419. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)

The real-time pulse unit (RPU) measures pulse intervals and frequencies, and outputs programmable pulses. Itis capable of 16-bit measurement. It can also generate various types of pulses, such as interval pulse and one-shotpulse.9.1 Features

Timer 0 (TM0)

•16-bit timer/event counter

•Two count clock sources (system clock frequency division selected or external pulse input)•Four capture/compare registers•Count clear pin (TCLR)•Five interrupt sources•Two external pulse outputsTimer 1 (TM1)•16-bit interval timer

•Count clock generated by dividing the system clock frequency•Compare register•Interrupt source

Figure 9-1. Timer 0 (16-Bit Timer/Event Counter)

TCLREdgedetectionClear and startClear and startφ/2φ/4TIφmφφφφNote 2mm/4m/8m/16Note 1TM0 (16 bits)INTOV0EdgedetectionEdgedetectionEdgedetectionEdgedetectionEdgedetectionSRINTCC00INTCC01CC00CC01CC02CC03QINTP00INTP01INTP02INTP03TO00Note 3QSRQTO01Note 3QINTCC02INTCC03Notes 1. Internal count clock 2. External count clock 3. A reset takes precedence.φ: System clockRemark 41

µPD70741Figure 9-2. Timer 1 (16-Bit Interval Timer)

φ/2φ/4φ/8φmφm/16Noteφm/32TM1 (16 bits)Clear and startCM1INTCM1Note Internal count clockφ: System clockRemark 42

µPD7074110. WATCHDOG TIMER FUNCTIONS

The watchdog timer is intended to prevent program crash and deadlock.10.1 Features

•The following three different time-out time values can be specified: 10.5 ms, 41.9 ms, and 167.8 ms (when

system clock φ = 25 MHz)

•Watchdog timer time-out output (WDTOUT)

Figure 10-1. Watchdog Timer Block Diagram

φFrequencydividerφ/210φ/212φ/214Watchdogtimer(8 bits)Time-outActive timer(5 bits)ClearTime-outRSQWDTOUTWDTM register CLR bitRESETSTOPOscillationsettling time control circuitφ: System clockRemark 43

µPD70741(1)Watchdog timer

One of the watchdog timer functions is to secure the oscillation settling time of the system clock. When the systemis reset or placed in STOP mode, the timer is cleared to 00H.The watchdog timer behaves in the standby modes as follows:(a)STOP mode

The watchdog timer stops counting. When the system is released from STOP mode, the timer value iscleared.

The watchdog timer starts counting at 00H, and keeps counting until a time-out occurs. A time-outsignal is supplied to the oscillation settling time control circuit, thus starting to supply the system clockpulse. At this point, the WDTOUT pin does not become active. If the system is released from STOPmode by the NMI pin, the timer continues counting.(b)IDLE mode

The watchdog timer stops counting, but it holds the count value.

When the system is released from IDLE mode, the watchdog timer resumes counting by starting at thecurrent count value.(c)HALT mode

The watchdog timer continues counting.

(2)Active timer

The watchdog timer outputs the WDTOUT signal when it times out. The active timer retains this signal for 32clock cycles.

When the watchdog timer times out, it can cause a system reset by connecting the WDTOUT and RESET pinsthrough an external circuit.10.2 Operation

The watchdog timer indicates that the program or system is running normally, by keeping the WDTOUT pin frombecoming active.

To use the watchdog timer, it is necessary to specify the WDTM register so that the watchdog timer is cleared(restarted to count) at constant intervals during program execution or at the beginning of a subroutine. If the watchdogtimer expires because it is not cleared within a specified period of time, the WDTOUT pin becomes active, indicatinga program failure. In addition, the WDT time-out flag (OV) is set. This flag is cleared by clearing the WDT counter.To use a watchdog timer time-out as an interrupt source, it is necessary to connect the WDTOUT pin to an externalinterrupt request pin (INTPn or NMI) through an external circuit.

µPD7074111. PORT FUNCTIONS

The V821 pins are dual-function pins that can function as both port and control pins. See Chapter 1 for detailsof each pin.11.1 Features

•10 input/output ports (P00 to P09)

Figure 11-1. Configuration

WriteMode (PM×)Internal addressLatchI/ORead45

µPD7074112. CLOCK GENERATION FUNCTIONS

The clock generator generates and controls the internal clock pulse (φ) for the CPU and other built-in hardwareunits.

12.1 Features

Frequency multiplication (5 times) using a PLL (phase locked loop) synthesizerClock sources

•Resonator-based oscillation:fXX = φ/5•External clock•External clockClock output control

Figure 12-1. Configuration:fXX = φ/5

(PLL mode)(PLL mode)

:fXX = 2 × φ(direct mode)

RESETTCLRLatchDirect mode(fXX)X1 (fXX)X2OSC12PLL synthesizer12(10 • fXX)PLL modeCLKOUTφSTOP modeφφ: Internal clock frequency ( = 1/2•10•fXX: PLL mode)φXX: Direct mode) Internal clock frequency ( = 1/2•fOSC: Oscillator (only for the PLL mode)46

µPD7074113. STANDBY FUNCTIONS

The V821 supports three standby modes to suppress power dissipation. In these standby modes, the operationof the clock is controlled. The HALT instruction is used to select a standby mode. Mode switching is controlled usingthe standby control register.13.1 Features

HALT mode(Only the CPU clock stops.)

IDLE mode(The CPU and peripheral operation clocks stop. The clock generator continues to operate.)STOP mode(The entire system, including the clock generator, stops.)13.2 Standby Mode

The standby modes of the V821 are detailed below.(1)HALT mode

In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but the CPU clock stops.Clock supply to other built-in peripheral functions continues to allow them to keep running. Intermittent operationachieved using this standby mode in conjunction with the ordinary operation mode can reduce the total powerdissipation of the system.(2)IDLE mode

In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but internal system clocksupply is stopped to bring the entire system to a stop.

When the system is released from IDLE mode, it is unnecessary to secure oscillation settling time for the oscillator,and therefore it is possible for the system to shift to the ordinary operation quickly.

For the oscillation settling time and current drain, IDLE mode lies in between STOP and HALT modes. IDLEmode is suitable for an application where it is necessary to cut the oscillation settling time using a low currentdrain mode.(3)STOP mode

In this mode, the clock generator (oscillator and PLL synthesizer) is stopped to bring the entire system to a stop.This mode can generate an ultra-low power dissipation condition; only leak current occurs.(a)PLL mode

In this mode, the PLL synthesizer clock output is stopped simultaneously with the oscillator. After thesystem is released from STOP mode, it is necessary to allow oscillation settling time for the oscillator.Some programs require a PLL lock-up time.(b)Direct mode

In the direct mode, it is unnecessary to secure lock-up time.

Table 13-1 lists the operation of the clock generator in the ordinary, HALT, IDLE, and STOP modes. An effectivelow power dissipation system can be implemented by combining and switching these modes.

µPD70741Table 13-1. Clock Generator Operation under Standby Control

Clock source

Standby mode

Oscillator(OSC)

ooo×××××××××

PLL

synthesizer

ooo×ooo×××××

Clock supplyto the pe-ripheral I/O

oo××oo××oo××

Clock supplyto the CPU

o×××o×××o×××

PLL modeResonator-basedoscillation

OrdinaryHALTIDLESTOP

External clockOrdinaryHALTIDLESTOP

Direct modeOrdinaryHALTIDLESTOP

Remarko:Operating

×:Stopped

Table 13-2. Operation Status in HALT, IDLE, or STOP Mode

Function

Clock generatorInternal system clockCPUI/O line

Peripheral functionInternal dataA0-A23, UBED0-D15CS0-CS3IORD, IOWRMWR/LMWR, UMWRREFRQ, RAS, LCAS, UCASHLDRQCLKOUT

1 (other than during CBRrefresh)NoteOperatingNote

Clock output (when the clock output is not inhibited)

CBR self-refreshNote

CBR self-refreshStopped1

OperatingOperatingStoppedRetainedOperating

StoppedStopped

HALT mode

IDLE mode

STOP mode

Stopped

All internal data, such as in CPU registers is retained.PC outputNoteHigh impedance1Note

PC output

Note High impedance when HLDAK = 048

µPD7074114. RESET FUNCTIONS

Inputting a low level to the RESET pin triggers a system reset, thus initializing the on-chip hardware.

When the RESET pin is driven from a low level to a high, the CPU starts program execution. The registers shouldbe initialized in a program as required.14.1

Features

The reset pin is provided with a noise suppressor circuit based on an analog delay (60 to 300 ns).

14.2

Pin Functions

Table 14-1 lists the state of the output from each pin during a system reset. The output state is retained duringthe entire reset period.

After the RESET pin is kept at a low level for 30 clock cycles, if the HLDRQ signal is inactive, a memory read cycleis started to fetch an instruction.

Even during a reset period (when the RESET pin is kept at a low level), activating the HLDRQ signal can placethe bus on hold. The state of each pin with the bus put on hold during a reset is basically the same as that with thebus put on hold during a non-reset period.

The HLDRQ signal should be kept inactive during a power-on reset.

It is necessary to provide a pull-up or pull-down resistor to the pins that become high impedance during a reset.If no pull-up or pull-down resistor is provided to these pins, memory may be damaged when the pins are driven tohigh impedance.

The CLKOUT pin supplies clock pulses even during a reset.

Table 14-1. Output State of Each Pin during a Reset

A0-A23D0-D15P00/TCLRP01/DREQ0P02/DACK0P03/DREQ1P04/DACK1P05/SIP06/SOP07/SCLKP08/TXD/UBEP09/RXD/TC

Operation stateNot definedHigh impedance

HLDAKMRDLMWR/WEUMWRIORDIOWRCS1-CS3RASLCASUCASCS0/REFRQBLOCK/WDTOUT

Low level

Operation stateHigh level

µPD7074115. INSTRUCTION SET

15.1 Instruction Format

The V821 instructions are formatted in either 16 bits or 32 bits. Examples of the 16-bit format instruction arebinomial operation, control, and conditional branch; those for the 32-bit format are load/store, I/O manipulate, 16-bit immediate, jump & link, and extended operations.

Some instructions have an unused field. However, do not write a program that uses this field because it is reservedfor future use. This unused field must be set to zeros.Instructions are stored in memory in the following manner.

•The lower half of an instruction, that is, the half which includes bit 0, is stored at the lower address.•The higher half of an instruction, that is, the half which includes bit 15 or 31, is stored at the higher address.(1)reg-reg instruction format (Format I)

This format consists of one 6-bit field to hold an operation code and two 5-bit fields to specify general-purposeregisters as instruction’s operands. 16-bit instructions use this format.

15opcode109reg2reg10(2)imm-reg instruction format (Format II)

This format consists of one 6-bit field to hold an operation code, one 5-bit field to hold an immediate data, andone field to specify a general-purpose register as an operand. 16-bit instructions use this format.

15opcode109reg2imm0(3)Conditional branch instruction format (Format III)

This format consists of one 3-bit field to hold an operation code, one 4-bit field to hold a condition code, and one9-bit field to hold a branch displacement (with its LSB masked to 0). 16-bit instructions use this format.

151312cond98disp00opcode50

µPD70741(4)Intermediate jump instruction format (Format IV)

This format consists of one 6-bit field to hold an operation code and one 26-bit field to hold a displacement (withits LSB masked to 0). 32-bit instructions use this format.

15opcode109031disp160(5)3-operand instruction format (Format V)

This format consists of one 6-bit field to hold an operation code, two fields to specify general-purpose registersas operands, and one 16-bit field to hold an immediate data. 32-bit instructions use this format.

15opcode109reg2reg1031imm16(6)Load/store instruction format (Format VI)

This format consists of one 6-bit field to hold an operation code, two fields to specify a general-purpose register,and one 16-bit field to hold a displacement. 32-bit instructions use this format.

15opcode109reg2reg1031disp16(7)Extension instruction format (Format VII)

This format consists of one 6-bit field to hold an operation code, two 5-bit fields to specify general-purposeregisters as operands, and one 6-bit field to hold an sub-operation code. 32-bit instructions use this format.

15opcode109reg2reg1031sub-opcode2625RFU1651

µPD7074115.2 Instruction Mnemonic (In Alphabetical Order)The list of mnemonics is shown below.

This section lists the instructions incorporated in the V821 along with their operations. The instructions are listedin the instruction mnemonic’s alphabetical order to allow users to use this section as a quick reference or dictionary.The conventions used in the list are shown below.

Instruction mnemonicOperand (s)FormatCYOVSZInstruction functionLegendADDreg1, reg2I****Mnemonic of instructionIdentifier of operandInstruction format(See Section 15.1.)Flag operation-Remains unchanged*Inverts the previous value0Changes to 01Changes to 1Identifierreg1reg2imm5imm16disp9disp16disp26regIDvector adrDescriptionGeneral-purpose register (Used as a source register)General-purpose register (Used mainly as a destination register and occasionally as a source register)5-bit immediate16-bit immediate9-bit displacement16-bit displacement26-bit displacementSystem register numberTrap handler address that corresponds to a trap vector52

µPD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (1/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicADD

ADDADDF.SADDIANDANDBSUANDIANDNBSUBCBEBGEBGT

reg1, reg2

imm5, reg2reg1, reg2imm16, reg1, reg2reg1, reg2-imm16, reg1, reg2-disp9disp9disp9disp9

II*VII*V*I-II-V-II-III-III-III-III

***

0**

***

0**

---

00*

---

----------

Addition:Adds the word data in the reg2-specified register andthe word data in the reg1-specified register, thenstores the result into the reg2-specified register.Addition:Sign-extends the 5-bit immediate data to 32 bits, andadds the extended immediate data and the word datain the reg2-specified register, then stores the resultinto the reg2-specified register.

Floating-point addition:Adds the single-precision floating-point data in thereg2-specified register and the single-precision floating-point data in the reg1-specified register, then restoresthe result into the reg2-specified register while changingflags according to the result.

Addition:Sign-extends the 16-bit immediate data to 32 bits, andadds the extended immediate data and the word datain the reg1-specified register, then stores the resultinto the reg2-specified register.

AND:Performs the logical AND operation on the word datain the reg2-specified register and the word data in thereg1-specified register, then stores the result into thereg2-specified register.

Transfer after ANDing bit strings:Performs a logical AND operation on a source bitstring and a destination bit string, then transfers theresult to the destination bit string.

AND:Sign-extends the 16-bit immediate data to 32 bits, andperforms a logical AND operation on the extendedimmediate data and the word data in the reg1-specifiedregister, then stores the result into the reg2-specifiedregister.

Transfer after NOTting a bit string then ANDing it withanother bit string:Performs a logical AND operation on a destination bitstring and the 1’s complement of a source bit string,then transfers the result to the destination bit string.Conditional branch (if Carry):PC relative branch

Conditional branch (if Equal):PC relative branch

Conditional branch (if Greater than or Equal):PC relative branch

Conditional branch (if Greater than):PC relative branch

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (2/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicBHBLBLEBLTBNBNCBNEBNHBNLBNVBNZBPBRBVBZCAXICMP

CMPCMPF.S

disp9disp9disp9disp9disp9disp9disp9disp9disp9disp9disp9disp9disp9disp9disp9

disp16 [reg1], reg2reg1, reg2

imm5, reg2reg1, reg2III-III-III-III-III-III-III-III-III-III-III-III-III-III-III-VI*I

II*VII*---------------------------------------------****

***

0**

Conditional branch (if Higher):PC relative branch

Conditional branch (if Lower):PC relative branch

Conditional branch (if Less than or Equal):PC relative branch

Conditional branch (if Less than):PC relative branch

Conditional branch (if Negative):PC relative branch

Conditional branch (if Not Carry):PC relative branch

Conditional branch (if Not Equal):PC relative branch

Conditional branch (if Not Higher):PC relative branch

Conditional branch (if Not Lower):PC relative branch

Conditional branch (if Not Overflow):PC relative branch

Conditional branch (if Not Zero):PC relative branch

Conditional branch (if Positive):PC relative branchUnconditional branch:PC relative branch

Conditional branch (if Overflow):PC relative branch

Conditional branch (if Zero):PC relative branch

Inter-processor synchronization in a multi-processorsystemComparison:Subtracts the word data in the reg1-specified registerfrom that for reg2 for comparison, then changes flagsaccording to the result.

Comparison:Sign-extends the 5-bit immediate data to 32 bits, andsubtracts the extended immediate data from the worddata in the reg2-specified register for comparison,then changes flags according to the result.

Floating-point comparison:Subtracts the single-precision floating-point data inthe reg1-specified register from that for reg2 forcomparison, then changes flags according to theresult.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (3/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicCVT.SW

reg1, reg2

CVT.WSreg1, reg2DIVreg1, reg2DIVF.Sreg1, reg2DIVUreg1, reg2HALT-IN.B

disp16 [reg1], reg2

IN.Hdisp16 [reg1], reg2VII

-VII*I-VII*I-II-VI

VI-0

0**

***

0**

----

---

Data conversion from floating-point to integer:Converts the single-precision floating-point data in thereg1-specified register into an integer data, then storesthe result into the reg2-specified register while changingflags according to the result.

Data conversion from integer to floating-point:Converts the integer data in the reg1-specified registerinto a single-precision floating-point data, then storesthe result into the reg2-specified register while changingflags according to the result.

Signed division:Divides the word data in the reg2-specified register bythat for reg1 with their sign bits validated, then storesthe quotient into the reg2-specified register and theremainder into r30. Division is performed so that thesign of the remainder matches that of the dividend.Floating-point division:Divides the single-precision floating-point data in thereg2-specified register by that for reg1, then stores theresult into the reg2-specified register while changingflags according to the result.

Unsigned division:Divides the word data in the reg2-specified register bythat for reg1 with their data handled as unsigned data,then stores the quotient into the reg2-specified registerand the remainder into r30. Division is performed sothat the sign of the remainder matches that of thedividend.Processor stopPort input:Sign-extends the 16-bit displacement to 32 bits, andadds the extended displacement and the content ofthe reg1-specified register to generate a 32-bit unsignedport address, then reads the byte data located at thegenerated port address, zero-extends the byte data to32 bits, and stores the result into the reg2-specifiedregister.

Port input:Sign-extends the 16-bit displacement to 32 bits, andadds the extended displacement and the content ofthe reg1-specified register to generate a 32-bit unsignedport address, then reads the halfword data located atthe generated port address while masking the address’sbit 0 to 0, zero-extends the halfword data to 32 bits,and stores the result into the reg2-specified register.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (4/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicIN.W

disp16 [reg1], reg2

JALdisp26JMP[reg1]JRdisp26LD.Bdisp16 [reg1], reg2LD.Hdisp16 [reg1], reg2LD.Wdisp16 [reg1], reg256

-IV-I-IV-VI-VI-VI-------

---

Port input:Sign-extends the 16-bit displacement to 32 bits, andadds the extended displacement and the content ofthe reg1-specified register to generate a 32-bit unsignedport address, then reads the word data located at thegenerated address while masking the address’s bits0 and 1 to 0, and stores the word into the reg2-specified register.

Jump and link:Increments the current PC by 4, then saves it into r31,and sign-extends the 26-bit displacement to 32 bitswhile masking the displacement’s bit 0 to 0, adds theextended displacement and the PC value, loads thePC with the addition result, so that the instructionstored at the PC-pointing address is executed next.Register-indirect unconditional branch:Loads the PC with the jump address value in the reg1-specified register while masking the value’s bit 0 to 0,so that the instruction stored at the address pointedby the reg1-specified register is executed next.Unconditional branch:Sign-extends the 26-bit displacement to 32 bits whilemasking bit 0 to 0, adds the result with the current PCvalue, and loads the PC with the addition result so thatthe instruction stored at the PC-pointing address isexecuted next.

Byte load:Sign-extends the 16-bit displacement to 32 bits, andadds the result with the content of the reg1-specifiedregister to generate the 32-bit unsigned address, thenreads the byte data located at the generated address,sign-extends the byte data to 32 bits, and stores theresult into the reg2-specified register.

Halfword load:Sign-extends the 16-bit displacement to 32 bits, andadds the result with the content of the reg1-specifiedregister to generate a 32-bit unsigned address whilemasking its bit 0 to 0, then reads the halfword datalocated at the generated address, sign-extends thehalfword data to 32 bits, and stores the result into thereg2-specified register.

Word load:Sign-extends the 16-bit displacement to 32 bits andadds the result with the content of the reg1-specifiedregister to generate a 32-bit unsigned address whilemasking bits 0 and 1 to 0, then reads the word datalocated at the generated address and stores the datainto the reg2-specified register.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (5/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicLDSR

MOVMOVMOVBSUMOVEAMOVHIMULMULF.SMULUNOPNOT

reg2, regID

reg1, reg2imm5, reg2-imm16, reg1, reg2imm16, reg1, reg2reg1, reg2reg1, reg2reg1, reg2-reg1, reg2

I-II-II-V-V-I-VII*I-III-I

---

***

0**

***

---0

Loading system register:Transfers the word data in the reg2-specified registerto the system register specified with the system registernumber (regID).

Transferring data:Loads the reg2-specified register with the word datain of the reg1-specified register.

Transferring data:Sign-extends the 5-bit immediate data to 32 bits, thenloads the reg2-specified register with the extendedimmediate data.

Transferring bit strings:Loads the destination bit string with the source bitstring.

Addition:Sign-extends the 16-bit immediate data to 32 bits,adds it with the word data in the reg1-specified register,then stores the addition result into reg2.

Addition:Appends 16-bit zeros below the 16-bit immediate datato form a 32-bit word data, then adds it with the worddata in the reg1-specified register, and stores theresult into the reg2-specified register.

Signed multiplication:Signed-multiplies the word data in the reg2-specifiedregister by that for reg1, then separates the -bit(double-word) result into two 32-bit data, and storesthe higher 32 bits into r30 and the lower 32 bits intothe reg2-specified register.

Floating-point multiplication:Multiplies the single-precision floating-point data inthe reg2-specified register by that for reg1, then storesthe result into the reg2-specified register while changingflags according to the result.

Unsigned multiplication:Multiplies the word data in the reg2-specified registerby that for reg1 while handling these data as unsigneddata, then separates the -bit (double-word) resultinto two 32-bit data, and stores the higher 32 bits intor30 and the lower 32 bits into the reg2-specifiedregister.No operationLogical NOT:Obtains the 1’s complement (logical NOT) of thecontent of the reg1-specified register, then stores theresult into the reg2-specified register.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (6/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicNOTBSU

ORORBSUORIORNBSUOUT.BOUT.HOUT.W58

-reg1, reg2-imm16, reg1, reg2-reg2, disp16 [reg1]reg2, disp16 [reg1]reg2, disp16 [reg1]II

-I-II-V-II-VI-VI-VI----0**

---

0**

---

Transfer after NOTting a bit string:Obtains the 1’s complement (all bits inverted) of thesource bit string, then transfers the result to thedestination bit string.

OR:Performs a logical OR operation on the word data inthe reg2-specified register and that for reg1, thenstores the result into the reg2-specified register.Transfer after ORing bit strings:Performs a logical OR operation on the source anddestination bit strings, then transfers the result to thedestination bit string.

OR:Zero-extends the 16-bit immediate data to 32 bits,performs a logical OR operation on the extended dataand the word data in the reg1-specified register, thenstores the result into the reg2-specified register.Transfer after NOTting a bit string and ORing it withanother bit string:Obtains the 1’s complement (logical NOT) of thesource bit string, performs a logical OR operation onthe NOTted bit string and the destination bit string,then transfers the result to the destination bit string.Port output:Sign-extends the 16-bit displacement to 32 bits, addsthe extended value and the content of the reg1-specified register to generate a 32-bit unsigned portaddress, then outputs the lowest 8 bits (= 1 byte) ofthe reg2-specified register onto the port pinscorresponding to the generated port address.Port output:Sign-extends the 16-bit displacement to 32 bits, addsthe extended value and the content of the reg1-specified register to generate a 32-bit unsigned portaddress with its bit 0 masked to 0, then outputs thelowest 16 bits (= 1 halfword) of the reg2-specifiedregister onto the port pins corresponding to the generatedport address.

Port output:Sign-extends the 16-bit displacement to 32 bits, addsthe extended value and the content of the reg1-specified register to generate a 32-bit unsigned portaddress with its bits 0 and 1 masked to 0, then outputsthe 32 bits (= 1 word) of the reg2-specified registeronto the port pins corresponding to the generated portaddress.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (7/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicRETI

SARSARSCH0BSUSCH0BSDSCH1BSUSCH1BSD

SETFSHL-reg1, reg2imm5, reg2----

imm5, reg2reg1, reg2II

I*II*II-II-II-II

II-I**

0**

--*--*

----

---

0**

Return from a trap or interrupt routine:Reads the restore PC and PSW from the systemregisters and loads them to the due places to returnfrom a trap or interrupt routine to the original operationflow.

Arithmetic right shift:Shifts every bit of the word data in the reg2-specifiedregister to the right by the number of times specifiedwith the reg1-specified register’s lowest 5 bits, thenstores the result into the reg2-specified register. Inarithmetic right shift operations, the MSB is loadedwith the LSB value at each shift.

Arithmetic right shift:Zero-extends the 5-bit immediate data to 32 bits, shiftsevery bit of the word data in the reg2-specified registerto the right by the number of times specified with theextended immediate data, then stores the result intothe reg2-specified register.

Searching 0s in a bit string:Searches “0” bits in the source bit string, and loads r30and r27 with the address of the bit next to the firstdetected “0” bit, then r29 with the number of bitsskipped until the first “0” bit is detected, and r28 withthe value subtracted by the r29 value.

Searching 1s in a bit string:Searches 1s in the source bit string, and loads r30 andr27 with the bit address next to the first detected “1”bit, then r29 with the number of bits skipped until thefirst “1” is detected, and r28 with the value subtractedby the r29 value.

Flag condition setting:Sets the reg2-specified register to 1 if the conditionflag value matches the lowest 4 bits of the 5-bitimmediate data, and sets the reg2-specified registerto 0 when they do not match.

Logical left shift:Shifts every bit of the word data in the reg2-specifiedregister to the left by the number of times specifiedwith the reg1-specified register’s lowest 5 bits, thenstores the result into the reg2-specified register. Inlogical left shift operations, the LSB is loaded with 0at each shift.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (8/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicSHL

imm5, reg2

SHRreg1, reg2SHRimm5, reg2ST.Breg2, disp16 [reg1]ST.Hreg2, disp16 [reg1]ST.Wreg2, disp16 [reg1]STSRregID, reg2SUBreg1, reg260

I*II*VI-VI-VI-II-I*0

0**

---

***

Logical left shift:Zero-extends the 5-bit immediate data to 32 bits, shiftsevery bit of the word data in the reg2-specified registerto the left by the number of times specified by theextended immediate data, then stores the result intothe reg2-specified register.

Logical right shift:Shifts every bit of the word data in the reg2-specifiedregister to the right by the number of times specifiedwith the reg1-specified register’s lowest 5 bits, thenstores the result into the reg2-specified register. Inlogical right shift operations, the MSB is loaded with0 at each shift.

Logical right shift:Zero-extends the 5-bit immediate data to 32 bits, shiftsevery bit of the word data in the reg2-specified registerto the right by the number of times specified by theextended immediate data, then stores the result intothe reg2-specified register.

Byte store:Sign-extends the 16-bit displacement to 32 bits andadds the 32-bit displacement and the content of thereg1-specified register to generate a 32-bit unsignedaddress, then transfers the reg2-specified register’slowest 8 bits to the generated address.

Halfword store:Sign-extends the 16-bit displacement to 32 bits withits bit 0 masked to 0, and adds the content of the reg1-specified register and the 32-bit displacement to generatea 32-bit unsigned address, then transfers the reg2-specified register’s lower 16 bits to the generatedaddress.

Word store:Sign-extends the 16-bit displacement to 32 bits withits bits 0 and 1 masked to 0, and adds the reg1-specified register and the 32-bit displacement to generatea 32-bit unsigned address, then transfers the worddata of the reg2-specified register to the generatedaddress.

Storing system register contents:Loads the reg2-specified register with the content ofthe system register specified by the system registernumber (regID).

Subtraction:Subtracts the word data in the reg1-specified registerfrom that in the reg2-specified register, then stores theresult into the reg2-specified register.

µPD70741Table 15-1. Instruction Mnemonics (In Alphabetical Order) (9/9)

InstructionOperand (s)

Format

CYOV

Instruction function

mnemonicSUBF.S

TRAPTRNC.SWXORXORBSUXORIXORNBSUreg1, reg2

vectorreg1, reg2reg1, reg2-imm16, reg1, reg2-VII

II-VII-I-II-V-II-0

---

0**

---

0**

---

Floating-point subtraction:Subtracts the single-precision floating-point data inthe reg1-specified register from that for reg2, thenstores the result into the reg2-specified register whilechanging flags according to the result.

Software trap:Jumps to a trap handler address according to thevector-specified trap vector (from 0 to 31) to start anexception handling after completing all necessarysaving and presetting procedures as follows:

(1)Saving the restore PC and PSW into the FEPC

and FEPSW system registers, respectively, if thePSW’s EP flag = 1, or into the EIPC and EIPSWsystem registers, respectively, if EP = 0

(2)Setting an exception code into the ECR’s FECC

and FEPSW flags if the PSW’s EP flag = 1, or intothe ECR’s EICC if EP = 0

(3)Setting the PSW’s ID flag and clearing the PSW’s

AE flag

(4)Setting the PSW’s NP flag if the PSW’s EP flag

= 1, or setting the PSW’s ID flag if EP = 0Conversion from floating-point data to integer:Converts the single-precision floating-point data in thereg1-specified register into an integer data, then storesthe result into the reg2-specified register while changingflags according to the result.

Exclusive OR:Performs a logical exclusive-OR operation on theword data in the reg2-specified register and that forreg1, then stores the result into the reg2-specifiedregister.

Transfer of exclusive ORed bit string:Performs a logical exclusive-OR operation on thesource and destination bit strings, then transfers theresult to the destination bit string.

Exclusive OR:Zero-extends the 16-bit immediate data to 32 bits andperforms a logical exclusive-OR operation on theextended immediate data and the word data in thereg1-specified register, then stores the result into thereg2-specified register.

Transfer after exclusive-ORing a NOTted bit stringand another bit string:Obtains the 1’s complement (NOT) of the source bitstring, and exclusive-ORs it with the destination bitstring, then transfers the result to the destination bitstring.

µPD7074116. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter

Supply voltageInput voltageClock input voltageOutput voltage

Operating ambient temperatureStorage temperature

SymbolVDDVIVKVOTATstg

VDD = +5.0 V ± 10 %VDD = +5.0 V ± 10 %VDD = +5.0 V ± 10 %

Conditions

Rating-0.5 to +7.0-0.5 to VDD + 0.3-0.5 to VDD + 0.3-0.5 to VDD + 0.3-40 to +85-65 to +150

UnitVVVV°C°C

Cautions1.Do not connect an output (or input/output) pin of an IC device directly to any other output (or

input/output) pin of the same device, or directly to VDD , VCC, or GND. Open-drain pins andopen-collector pins can, however, be connected directly to each other. Note, however, thatthese restrictions do not apply to those high-impedance pins that are provided with an externalcircuit for which timings have been designed such that no output contention occurs.2.Absolute maximum ratings are rated values beyond which some physical damages may becaused to the product; if any of the parameters in the table above exceeds its rated value evenfor a moment, the quality of the product may deteriorate. Be sure to use the product with amoderate value within the rated range.

The standard values and conditions listed in the DC and AC characteristics tables indicatethe ranges in which the normal operation and performance of the product can be guaranteed.

DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = +5.0 V ± 10 %)

Parameter

Low-level clock input voltageHigh-level clock input voltageLow-level input voltage

SymbolVKLVKHVIL1VIL2

High-level input voltage

VIH1VIH2

Schmitt-triggered input hysteresis widthVSHLow-level output voltageHigh-level output voltage

VOLVOH

Other than RESET, NMI, and INTPnRESET, NMI, and INTPnOther than RESET, NMI, and INTPnRESET, NMI, and INTPnRESET, NMI, and INTPnIOL = 2.5 mAIOH = -2.5 mAIOH = -100 µA

Low-level input leakage currentHigh-level input leakage currentLow-level output leakage currentHigh-level output leakage currentSupply current

ILILILIHILOLILOHIDD

VIN = 0 VVIN = VDDVO = 0 VVO = VDD

Operation (f = 25 MHz)HALT (f = 25 MHz)IDLE (f = 25 MHz)STOP

1001845

0.7VDDVDD - 0.4

-1010-1010150453520

Conditions

MIN.-0..0-0.5-0.52.20.8VDD0.5

0.45

TYP.

MAX.+0.6VDD + 0.3+0.8+0.2VDDVDD + 0.3VDD + 0.3

UnitVVVVVVVVVV

µAµAµAµAmAmAmA

µA

µPD70741CAPACITANCE (TA = 25 °C, VDD = +5.0 V ± 10 %)

Parameter

Input capacitanceInput/output capacitance

SymbolCICIO

Conditions

fc = 1 MHz

MIN.

MAX.1515

UnitpFpF

µPD70741AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = +5.0 V ± 10 %)AC Test Input Waveform (Other than RESET, NMI, and INTPn)ParameterInput rise timeInput fall time12SymboltRtFConditionsMIN.MAX.77UnitnsnsVDD2.2 V0.8 V2Testpoints2.2 V0.8 V10 VAC Test Input Waveform (RESET, NMI, and INTPn)ParameterSchmitt-triggered input rise timeSchmitt-triggered input fall time34SymboltRStFSConditionsMIN.MAX.1010UnitnsnsVDD0.8VDD0.8 V4Testpoints0.8VDD0.8 V30 V AC Test Output Waveform

2.2 V0.8 VTestpoints2.2 V0.8 V Load Condition

V821 output pinCL = 100 pF

µPD70741RECOMMENDED OSCILLATION CIRCUIT(a)Connecting a ceramic resonator

(Murata Mfg. Co., Ltd.: TA = -20 to +80 °C, TDK Corp.: TA = -40 to +85 °C)

X1X2C1C2Cautions 1.The oscillation circuit should be placed as close to the X1 and X2 pins aspossible.2.Do not draw other signal lines in the area enclosed by broken lines.3.Throughly evaluate the matching between the PD70741 and the oscillationµcircuit.ManufacturerProduct nameOscillationfrequencyfxx (MHz)5.005.004.004.003.20Recommended circuitconstantsC1 (pF)30Built-in30C2 (pF)30Built-in30Oscillating voltagerangeMIN. (V)4....52.74.5CST3.20MGW3.20Built-inBuilt-in2.74.5CSA2.00MG0402.001001002.74.5CST2.00MG0402.00Built-inBuilt-in2.74.5TDKCCR5.0MC3FCR5.0MC5CCR4.0MC3FCR4.0MC5CCR3.2MC3CCR2.0MC335.005.004.004.003.202.00Built-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-inBuilt-in4....52.72.7MAX. (V)5.55.55.55.53.35.53.35.53.35.53.35.55.55.55.55.55.55.5Oscillation settling time (MAX.)TOST (ms)0.1020.1020.10.10.1020.1020.1020.1020.4980.4980.4980.4980.280.220.30.220.380.36Murata Mfg.Co., LtdCSA5.00MGCST5.00MGWCSA4.00MGCST4.00MGWCSA3.20MGBuilt-in Built-in303065

µPD70741(b)External clock input

X1X2OpenHigh-speed CMOS inverterExternal clock66

µPD70741(1) Clock input timing

ParameterExternal clock cycle5SymboltCYXConditionsDirect modePLL modeMIN.20200785785MAX.Unitns500nsnsnsnsnsExternal clock high-level width6tXKHDirect modePLL modeExternal clock low-level width7tXKLDirect modePLL modeExternal clock rise time8tXKRDirect modePLL mode315315nsnsnsnsExternal clock fall time9tXKFDirect modePLL mode56982.2 VX1 (input)0.8 V7(2) CLKOUT output timingParameterCLKOUT cycleCLKOUT high-level widthCLKOUT low-level widthCLKOUT rise time (0.8 V → 2.2 V)CLKOUT fall time (2.2 V → 0.8 V)101112SymboltCYKtKKHtKKLtKRtKFConditionsMIN.400.5T - 30.5T - 3MAX.100Unitnsnsns131455nsns Remark T: tCYK

101114132.2 VCLKOUT (output)0.8 V1267

µPD70741(3) Reset input timing

Parameter

Reset input width

15SymboltWRL

ConditionsPower-on resetSTOP modereleaseSystem reset

MIN.101030

MAX.UnitmsmstCYK

15RESET (input)68

µPD70741[MEMO]

µPD70741(4) SRAM, ROM, and I/O access timing

(a) Access timing (1/2)

Parameter

Address output delay (relative to CLKOUT↑)Address output hold time (relative to CLKOUT↑)CSn output delay (relative to CLKOUT↑)CSn output hold time (relative to CLKOUT↑)RD output delay (relative to CLKOUT↓)RD output hold time (relative to CLKOUT↑)WR output delay (relative to CLKOUT↓)WR output hold time (relative to CLKOUT↓)READY setup time (relative to CLKOUT↓)READY hold time (relative to CLKOUT↓)

Data output delay (from float, relative to CLKOUT)Data output hold time (to float, relative to CLKOUT↑)

161718Symbol

tDKAtHKAtDKCStHKCStDKRDtHKRDtDKWRtHKWRtSRYKtHKRYtLZKDTtHZKDT

ConditionsMIN.222222116622

MAX.1515151515151212

Unitnsnsnsnsnsnsnsnsnsns

1920212223242526271515

nsns

µPD70741(a) Access timing (2/2)

T1CLKOUT (output)16T2T217Note1819CS0-CS3 (output)2021IORD, MRD (output)2223IOWR, UMWR, LMWR (output)24252425READY (input)2627D0-D15 (input/output)(ADC = 0) (write)2627D0-D15 (input/output)(ADC = 1) (write)Note A0-A23 (output), UBE (output), BLOCK (output)Remark Broken lines indicate high impedance.71

µPD70741(b) Read timing (1/2)

Parameter

Read cycle timeAddress access time

Hold time from address to data inputCSn access time

Hold time from CSn to data input

Delay from CSn↑ to write data output (ADC = 0)Delay from CSn↑ to write data output (ADC = 1)RD access time

Hold time from RD to data inputRD pulse widthRD high-level width

Delay from RD↑ to write data output (ADC = 0)Delay from RD↑ to write data output (ADC = 1)Address valid time prior to RDCSn valid time prior to RD

28SymboltRCtAAtADHtCSAtCDHtDCD0tDCD1tRDAtRDHtRDPtRDRDHtDRD0tDRD1tARStCRS

ConditionsMIN.(n + 2)T - 10

MAX.Unitns

293031(n + 2)T - 25

(n + 2)T - 25

00.5T - 101T - 10

(n + 1.5)T - 25

0(n + 1.5)T - 70.5T - 100.5T - 101T - 100.5T - 70.5T - 7

nsnsnsnsnsnsnsnsnsnsnsnsnsns

3233343536373839404142RemarkT:tCYK

n:Wait state count

µPD70741(b) Read timing (2/2)

T1CLKOUT (output)2829T230A0-A23, UBE (output)4131323433CS0-CS3 (output)4235373638IORD, MRD (output)3940D0-D15 (input/output)(ADC = 0)D0-D15 (input/output)(ADC = 1)Remark Broken lines indicate high impedance.73

µPD70741(c) Write timing (1/2)

Parameter

Write cycle time

CSn setup time (relative to WR↑)Address setup time (relative to WR↑)Address valid time prior to WRAddress valid time after WRCSn valid time prior to WRCSn valid time after WRWR pulse width

Delay from WR↓ to data output (ADC = 0)Delay from WR↓ to data output (ADC = 1)Data output valid time prior to WR (ADC = 0)Data output valid time prior to WR (ADC = 1)Data output valid time after WR

43SymboltWCtCWtAWtAWStAWHtCWStCWHtWRPtWDS0tWDS1tDWS0tDWS1tDWH

ConditionsMIN.(n + 2)T - 10(n + 1.5)T - 10(n + 1.5)T - 10

0.5T - 70.5T - 100.5T - 70.5T - 10(n + 1)T - 7

-100.5T - 10(n + 1)T - 7(n + 0.5)T - 70.5T - 10

MAX.Unitnsnsnsnsnsnsnsnsnsnsnsnsns

444748495051525355RemarkT:tCYK

n:Wait state count

µPD70741(c) Write timing (2/2)

T1CLKOUT (output)4346T247A0-A23, UBE (output)4849CS0-CS3 (output)4450IOWR, UMWR, LMWR (output)515355D0-D15 (input/output)(ADC = 0)5255D0-D15 (input/output)(ADC = 1)Remark Broken lines indicate high impedance.75

µPD70741(5) DRAM access timing (when DRAM is directly connected)

(a) Read timing (normal access: off-page) (1/2)

Parameter

Delay from RD↑ to write data output (ADC = 0)Delay from RD↑ to write data output (ADC = 1)Read/write cycle timeRAS access timeCAS access timeAccess time from column addressOutput enable access time

Output buffer turn-off delay (relative to CAS)Output buffer turn-off delay (relative to MRD)RD setup time (relative to RAS↑)RAS precharge timeRAS pulse width

RAS column address delayRAS hold width (read)CAS pulse width (read)CAS hold widthRAS-CAS delay (read)RAS-CAS precharge timeCAS precharge timeRow address setup timeRow address hold time

Column address setup time (read)Column address hold time (read)

Column address read time relative to RASRead command setup timeRead command hold time

394056SymboltDRD0tDRD1tRCtRACtCACtAAtOEAtOFFtOEZtOEStRPtRAStRADtRSHtCAStCSHtRCDtCRPtCPtASRtRAHtASCtCAHtRALtRCStRCH

ConditionsMIN.0.5T - 101T - 10(w + 4)T - 10

MAX.Unitnsnsns

575859(w + 2)T - 20(w + 1)T - 20(w + 1)T - 31.5T - 20

001.5T1.5T - 10(w + 2.5)T - 20

0.5T - 3(w + 1.5)T - 20(w + 1)T - 15(w + 2)T - 151T - 151.5T0.5T - 100.5T - 150.5T - 70.5T - 15(w + 1)T - 15(w + 1.5)T0.5T0.5T - 15

0.5T + 7

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

60616263656667686970717273747576777879RemarkT:tCYK

w:Wait state count - 2

µPD70741(a) Read timing (normal access: off-page) (2/2)

T1CLKOUT (output)T2T2T273747576A0-A23, UBE(output)COL.ROW56COL.65RAS (output)717069686772UCAS, LCAS(output)66787779WE (output)58596061MRD (output)6339D0-D15(input/output)(ADC = 0)576240D0-D15(input/output)(ADC = 1)Remark Broken lines indicate high impedance.77

µPD70741(b) Write timing (normal access: off-page) (1/2)

Parameter

Read/write cycle timeRAS precharge timeRAS pulse width

RAS column address delayCAS hold width

RAS-CAS precharge timeRow address setup timeRow address hold time

Column address read time relative to RASRAS hold width (write)CAS pulse width (write)RAS-CAS delay (write)

Column address setup time (write)Column address hold time (write)Write command hold time

Write command read time relative to RASWrite command read time relative to CASData setup time (relative to CAS↓)Data hold time (relative to CAS↓)Write command setup time

56SymboltRCtRPtRAStRADtCSHtCRPtASRtRAHtRALtRSHtCAStRCDtASCtCAHtWCHtRWLtCWLtDStDHtWCS

ConditionsMIN.(w + 4)T - 101.5T - 10(w + 2.5)T - 20

0.5T - 3(w + 2)T - 15

1.5T0.5T - 150.5T - 7(w + 1.5)T1.5T - 201T - 15(w + 1)T - 15(w + 0.5)T - 15

1T - 150.5T - 101.5T1T0.5T - 151T - 200.5T - 15

MAX.Unitnsnsns

65660.5T + 7nsnsnsnsnsnsnsnsnsnsnsnsnsnsns

69717374778081828384858687881T + 10nsns

90RemarkT:tCYK

w:Wait state count - 2

µPD70741(b) Write timing (normal access: off-page) (2/2)

T1T2T2T2CLKOUT (output)73748384A0-A23, UBE(output)COL.ROW5666COL.6577RAS (output)7182698180UCAS, LCAS(output)9085WE (output)8786MRD (output)88D0-D15(input/output)(ADC = 0)88D0-D15(input/output)(ADC = 1)Remark Broken lines indicate high impedance.79

µPD70741(c) READY input timing (normal access)

Parameter

READY setup time (relative to CLKOUT↑)READY hold time (relative to CLKOUT↑)

24SymboltSRYKtHKRY

ConditionsMIN.66

MAX.Unitnsns

25T2CLKOUT (output)T2T2UCAS, LCAS (output)(read)UCAS, LCAS (output)(write)24252425READY (input)80

µPD70741[MEMO]

µPD70741(d) Read timing (high-speed page access: on-page) (1/2)

Parameter

Delay from RD↑ to write data output (ADC = 0)Delay from RD↑ to write data output (ADC = 1)CAS access time

Access time from column addressOutput enable access time

Output buffer turn-off delay (relative to CAS)Output buffer turn-off delay (relative to MRD)RD setup time (relative to RAS↑)RAS hold width (read)CAS pulse width (read)CAS precharge time

Column address setup time (read)Column address hold time (read)Cycle time in high-speed page modeAccess time from CAS prechargeRAS hold time relative to CAS prechargeRead command setup timeRead command hold time

3940SymboltDRD0tDRD1tCACtAAtOEAtOFFtOEZtOEStRSHtCAStCPtASCtCAHtPCtACPtRHCPtRCStRCH

ConditionsMIN.0.5T - 101T - 10

MAX.Unitnsns

585960(w + 1)T - 20(w + 1)T - 31.5T - 20

001.5T(w + 1.5)T - 20(w + 1)T - 150.5T - 100.5T - 15(w + 1)T - 151.5T - 10

2T - 20

2T0.5T0.5T - 15

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

61626367687275769192939495RemarkT:tCYK

w:0

µPD70741(d) Read timing (high-speed page access: on-page) (2/2)

T1CLKOUT (output)T27576A0-A23, UBE (output)COL.9367RAS (output)7261UCAS, LCAS (output)9455WE (output)59926361MRD (output)3940D0-D15 (input/output)(ADC = 0)6062D0-D15 (input/output)(ADC = 1)Remark Broken lines indicate high impedance.83

µPD70741(e) Write timing (high-speed page access: on-page) (1/2)

Parameter

CAS precharge timeRAS hold width (write)CAS pulse width (write)

Column address setup time (write)Column address hold time (write)Write command hold time

Write command read time relative to RASWrite command read time relative to CASData setup time (relative to CAS↓)Data hold time (relative to CAS↓)Write command setup time

Cycle time in high-speed page mode

7280SymboltCPtRSHtCAStASCtCAHtWCHtRWLtCWLtDStDHtWCStPC

ConditionsMIN.0.5T - 101.5T - 201T - 15(w + 0.5)T - 15

1T - 150.5T - 101.5T1T0.5T - 151T - 200.5T - 151.5T - 10

MAX.Unitnsnsnsnsnsnsnsnsns

818384858687801T + 10nsnsns

91RemarkT:tCYK

w:0

µPD70741(e) Write timing (high-speed page access: on-page) (2/2)

Note 1T1CLKOUT (output)8384Note 2T2T1T2T28384A0-A23, UBE (output)COL.COL.80RAS (output)91817281UCAS, LCAS (output)85908590WE (output)878687MRD (output)8888D0-D15 (input/output)Notes 1.When ADC = 1 and other than DRAM access was performed in theprevious cycle2.Other than the aboveRemark Broken lines indicate high impedance.85

µPD70741(6)DRAM access timing (when a control circuit is configured using a gate array or other devices)

(a) Read timing (normal access: off-page) (1/2)

Parameter

Address output delay (relative to CLKOUT)Address output hold time (relative to CLKOUT↑)RAS output delay (relative to CLKOUT↑)RAS output hold time (relative to CLKOUT↓)CAS output delay (relative to CLKOUT↑)CAS output hold time (relative to CLKOUT↑)MRD output delay (relative to CLKOUT↓)MRD output hold time (relative to CLKOUT↑)Data input setup time (relative to CLKOUT↑)Data input hold time (relative to CLKOUT↑)

969799100SymboltDKAtHKAtDKRAStHKRAStDKCAStHKCAStDKRDtHKRDtSDKtHKD

ConditionsMIN.2211112266

MAX.1515121212121515

Unitnsnsnsnsnsnsnsnsnsns

10110210310410586

µPD70741(a) Read timing (normal access: off-page) (2/2)

T1CLKOUT (output)96T2T2T2969697A0-A23, UBE(output)99COL.ROW98COL.RAS (output)100101UCAS, LCAS(output)WE (output)102103MRD (output)104105D0-D15(input/output)(ADC = 0)104105D0-D15(input/output)(ADC = 1)Remark Broken lines indicate high impedance.87

µPD70741(b) Write timing (normal access: off-page) (1/2)

Parameter

Address output delay (relative to CLKOUT↑)Address output hold time (relative to CLKOUT↑)RAS output delay (relative to CLKOUT↑)RAS output hold time (relative to CLKOUT↓)CAS output delay (relative to CLKOUT↑)CAS output hold time (relative to CLKOUT↑)WE output delay (relative to CLKOUT↓)WE output hold time (relative to CLKOUT↓)Data active delay (from float, relative to CLKOUT)Data inactive hold time (to float, relative to CLKOUT↑)

9697SymboltDKAtHKAtDKRAStHKRAStDKCAStHKCAStDKWEtHKWEtLZKDTtHZKDT

ConditionsMIN.2211111122

MAX.15151212121212121515

Unitnsnsnsnsnsnsnsnsnsns

9910010110610710810988

µPD70741(b) Write timing (normal access: off-page) (2/2)

T1CLKOUT (output)96T2T2T2969697A0-A23, UBE(output)99COL.ROW98COL.RAS (output)100101UCAS, LCAS(output)106107WE (output)MRD (output)108109D0-D15(input/output)(ADC = 0)108109D0-D15(input/output)(ADC = 1)Remark Broken lines indicate high impedance.

µPD70741(c) READY input timing (normal access)

Parameter

READY setup time (relative to CLKOUT↑)READY hold time (relative to CLKOUT↑)

24SymboltSRYKtHKRY

ConditionsMIN.66

MAX.Unitnsns

25T2CLKOUT (output)T2T2UCAS, LCAS (output)(read)UCAS, LCAS (output)(write)24252425READY (input)90

µPD70741[MEMO]

µPD70741 (d) Read timing (high-speed page access: on-page) (1/2)

Parameter

Address output delay (relative to CLKOUT)Address output hold time (relative to CLKOUT↑)CAS output delay (relative to CLKOUT↑)CAS output hold time (relative to CLKOUT↑)MRD output delay (relative to CLKOUT↓)MRD output hold time (relative to CLKOUT↑)Data input setup time (relative to CLKOUT↑)Data input hold time (relative to CLKOUT↑)

96SymboltDKAtHKAtDKCAStHKCAStDKRDtHKRDtSDKtHKD

ConditionsMIN.22112266

MAX.151512121515

Unitnsnsnsnsnsnsnsns

9710010110210310410592

µPD70741(d) Read timing (high-speed page access: on-page) (2/2)

T1CLKOUT (output)96T297A0-A23, UBE (output)COL.RAS (output)100101UCAS, LCAS (output)WE (output)102103MRD (output)104105D0-D15 (input/output)(ADC = 0)104105D0-D15 (input/output)(ADC = 1)Remark Broken lines indicate high impedance.93

µPD70741(e) Write timing (high-speed page access: on-page) (1/2)

Parameter

Address output delay (relative to CLKOUT↑)Address output hold time (relative to CLKOUT↑)CAS output delay (relative to CLKOUT↑)CAS output hold time (relative to CLKOUT↑)WE output delay (relative to CLKOUT↓)WE output hold time (relative to CLKOUT↓)Data active delay (from float, relative to CLKOUT)Data inactive hold time (to float, relative to CLKOUT↑)

96SymboltDKAtHKAtDKCAStHKCAStDKWEtHKWEtLZKDTtHZKDT

ConditionsMIN.22111122

MAX.1515121212121515

Unitnsnsnsnsnsnsnsns

9710010110610710810994

µPD70741 (e) Write timing (high-speed page access: on-page) (2/2)

Note 1T1CLKOUT (output)969697Note 2T2T1T2T297A0-A23, UBE (output)COL.COL.RAS (output)100101100101UCAS, LCAS (output)106107106107WE (output)MRD (output)108108109109D0-D15 (input/output)Notes 1.When ADC = 1 and other than DRAM access was performed in theprevious cycle2.Other than the aboveRemark Broken lines indicate high impedance.95

µPD70741(7)DRAM, CBR refresh timing

Parameter

READY setup time (relative to CLKOUT↑)READY hold time (relative to CLKOUT↑)RAS pulse widthCAS setup timeCAS hold timeRefresh pulse width

RAS precharge to CAS hold time

REFRQ active delay (relative to CLKOUT↑)REFRQ inactive delay (relative to CLKOUT↓)

24SymboltSRYKtHKRYtRAStCSRtCHRtREFtRPCtDKREFtHKREF

ConditionsMIN.66(w + 2.5)T - 201T - 20(w + 2.5)T - 20(w + 2.5)T - 204.5T - 20

MAX.Unitnsnsnsnsnsnsns

25651101111121131141151212

nsns

RemarkT: tCYK

w: Wait state count for CBR refresh

TICLKOUT (output)THTHTHTHTHTHTHTH114110112115REFRQ (output)65RAS (output)110111113UCAS, LCAS (output)24252425READY (input)Remark In the above timing chart, w = 1 is assumed.96

µPD70741(8)DRAM, CBR self-refresh timing

Parameter

CAS setup time

REFRQ active delay (relative to CLKOUT↑)REFRQ inactive delay (relative to CLKOUT↓)CAS hold timeRAS precharge time

Symbol

110114ConditionsMIN.1T - 2011-104.5T - 20

MAX.Unitns

tCSRtDKREFtHKREFtCHStRPS

1212

nsnsnsns

115116117RemarkT: tCYK

TICLKOUT (output)THTHTHTHTHTHTI114115REFRQ (output)110116117RAS (output)110116UCAS, LCAS (output)97

µPD70741(9)Page-ROM access timing (1/2)

Parameter

Hold time from address to data inputHold time from CSn to data inputHold time from RD to data inputOff-page address access timeOn-page address access timeOff-page CSn access timeOff-page RD access time

30SymboltADHtCDHtRDHtOFPAtONPAtOFCStOFRD

ConditionsMIN.000

MAX.Unitnsnsns

3236118(nOFF + 2)T - 25(nON + 2)T - 25(nOFF + 2)T - 25(nOFF + 1.5)T - 25nsnsnsns

119120121RemarkT

nON

:tCYK

:Wait state count for on-page access (nON = 0, 1)

nOFF:Wait state count for off-page access (nOFF = 0-7)

µPD70741(9)Page-ROM access timing (2/2)

Off-page accessT1CLKOUT (output)T2T2T2On-page accessT1T2A3-A23Note 1(output)118A0-A2Note 2(output)12011930CS3 (output)12132MRD (output)3036D0-D15(input/output)Notes 1.The address pins to be used vary with the settings of bits MA5 to MA3 of thepage-ROM configuration register (PRC).MA50001MA40011MA30111AddressA3-A23A4-A23A5-A23A6-A232.The address pins to be used vary with the settings of bits MA5 to MA3 of thepage-ROM configuration register (PRC).MA50001MA40011MA30111AddressA0-A2A0-A3A0-A4A0-A5Remark Broken lines indicate high impedance.99

µPD70741(10) Bus hold timing (1/2)

Parameter

HLDRQ setup time (relative to CLKOUT↓)HLDRQ hold time (relative to CLKOUT↓)HLDAK output delay (relative to CLKOUT↓)HLDAK output hold time (relative to CLKOUT↓)Delay from address float to HLDAK↓Delay from HLDAK↑ to address outputDelay from data float to HLDAK↓Delay from HLDAK↑ to data output

Symbol

122ConditionsMIN.66220.5T - 100.5T - 101.5T - 152T - 15

MAX.Unitnsns

tSHQKtHKHQtDKHAtHKHAtDAHAtDHAAtDDHAtDHAD

1231241251515

nsnsnsnsnsns

126127128129RemarkT: tCYK

100

µPD70741(10) Bus hold timing (2/2)

T1CLKOUT (output)122T2TITHTHTHTHTIT1123122HLDRQ (input)124125HLDAK (output)126127Note 1A0-A23 (output)Note 2MRD (output)CS3 (output)RAS (output)128129D0-D15 (input/output)Notes 1. The level existing immediately before the high-impedance state is held internally. 2. CS2-CS0 (output), UCAS (output), LCAS (output), LMWR/WE (output), UMWR (output), IORD (output), IOWR (output)Remark Broken lines indicate high impedance.101

µPD70741(11) DMAC timing (1/2)

Parameter

DREQn setup time (relative to CLKOUT↓)DREQn hold time (relative to CLKOUT↓)DACKn output delay (relative to CLKOUT↑)DACKn output hold time (relative to CLKOUT↑)TC output delay (relative to CLKOUT↑)TC output hold time (relative to CLKOUT↑)Delay from WR↑ to RD↑Delay from DACK↓ to RD↓Delay from DACK↓ to WR↓Delay from RD↑ to DACK↑Delay from WR↑ to DACK↑

Delay from CAS↓ to IOWR↑ (DRAM read)Delay from IOWR↑ to CAS↑ (DRAM read)Delay from IORD↓ to CAS↓ (DRAM write)

Symbol

130ConditionsMIN.6622220.5T - 100.5T - 100.5T - 10

-40.5T - 10(n + 1)T - 100.5T - 10(n + 0.5)T - 10

MAX.Unitnsns

tSDQKtHKDQtDKDAKtHKDAKtDKTCtHKTCtDWRDtDAKRDtDAKWRtRDDAKtWRDAKtCASWRtWRCAStRDCAS

13113213315151515

nsnsnsnsnsnsnsnsnsnsnsns

134135136137138139140141142143RemarkT:tCYK

n:DMA wait state count

102

µPD70741(11) DMAC timing (2/2)

T1CLKOUT (output)130131T2T1T2T2T3TIDREQ0, DREQ1(input)132133DACK0, DACK1(output)140A0-A23, UBE(output)137139MRD, IORD(output)138136136LMWR/WE, UMWR,IOWR (output)141142141142LCAS, UCAS(output) (read)143143LCAS, UCAS(output) (write)134135TC (output)103

µPD70741(12) INTPn input setup time, hold timeParameterINTPn input low setup timeINTPn input high setup timeINTPn input low pulse widthINTPn input high-level widthSymbol144ConditionsMIN.9922MAX.UnitnsnstCYKtCYKtSILKtSIHKtCYILtCYIH145146147CLKOUT (output)145147144146INTPn (input)(edge mode)144INTPn (input)(level mode)(13) NMI inputThe NMI pin incorporates a noise eliminator which is based on an analog delay (60 to 300 ns). The input setuptime and input hold time are not, therefore, specified for NMI.The NMI pin accepts a level input, such that the input level must be held until the acceptance of the input isconfirmed after a branch to the handler.

NMI (input)Analog delayInternal NMIsignalAnalog delayAnalog delayAfter confirming acceptance,de-activate NMI from the interrupthandler.CPU processingNormal processingNonmaskable interrupt handling104

µPD70741(14) RPU block timing

Parameter

Timer clock cycle timeTimer clock high-level widthTimer clock low-level widthTimer clear cycle timeTimer clear high-level widthTimer clear low-level widthTimer output high-level widthTimer output low-level width

Symbol

148ConditionsMIN.4224222T - 72T - 7

MAX.UnittCYKtCYKtCYKtCYKtCYKtCYKnsns

tTCYKtTKHtTKLtTCLRYtTCLRHtTCLRLtWTOHtWTOL

1491501511521531155RemarkT: tCYK

148149150TI (input)151152153TCLR (input)1155TO0n (input)105

µPD70741(15) CSI timing

(a) Master mode

Parameter

Serial clock cycle timeSerial clock high-level widthSerial clock low-level widthSI setup time (relative to SCLK↑)SI hold time (relative to SCLK↑)SO output delay (relative to SCLK↓)

Symbol

156157158ConditionsMIN.430302020

MAX.UnittCYKnsnsnsns

tCYSKtSKHtSKLtSSISKtHSKSItDSKSO

15916016130ns

(b) Slave mode

Parameter

Serial clock cycle timeSerial clock high-level widthSerial clock low-level widthSI setup time (relative to SCLK↑)SI hold time (relative to SCLK↑)SO output delay (relative to SCLK↓)

Symbol

156157158ConditionsMIN.430302020

MAX.UnittCYKnsnsnsns

tCYSKtSKHtSKLtSSISKtHSKSItDSKSO

15916016130ns

156158157SCLK (input/output)161SO (output)159160SI (input)Remark Broken lines indicate high impedance.106

17. PACKAGE DRAWINGS

100 PIN PLASTIC LQFP (FINE PITCH) (14×14)AB75517650CD10026125FGHIMJPKMNLNOTEEach lead centerline is located within 0.08 mm (0.003 inch) ofits true position (T.P.) at maximum material condition.

µPD70741detail of lead end

SQRITEMMILLIMETERSINCHESA16.00±0.200.630±0.008B14.00±0.200.551+0.009–0.008C14.00±0.200.551+0.009–0.008D16.00±0.200.630±0.008F1.000.039G1.000.039H0.22+0.05–0.040.009±0.002I0.080.003J0.50 (T.P.)0.020 (T.P.)K1.00±0.200.039+0.009–0.008L0.50±0.200.020+0.008–0.009M0.17+0.03–0.070.007+0.001–0.003N0.080.003P1.40±0.050.055±0.002Q0.10±0.050.004±0.002R3°+7–3°°3°+7–3°°S

1.60 MAX.

0.063 MAX.S100GC-50-8EU

107

µPD7074118. RECOMMENDED SOLDERING CONDITIONS

The µPD70741 should be soldered and mounted under the conditions recommended in the table below.For details of recommended soldering conditions, refer to the information document Semiconductor DeviceMounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 18-1. Surface Mounting Type Soldering Conditions

µPD70741GC-25-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 × 1.40 mm)

Soldering methodInfrared reflow

Soldering conditions

Package peak temperature: 235 °C, Duration: 30 sec. Max. (at 210 °C or above),Number of times: Twice Max., Time limit: 7 daysNote (thereafter 10 hours prebakingrequired at 125 °C)

Non-heat-resistant trays, such as magazine and taping trays, cannot be baked beforeunpacking.

Package peak temperature: 215 °C, Duration: 40 sec. Max. (at 200 °C or above),Number of times: Twice Max., Time limit: 7 daysNote (thereafter 10 hours prebakingrequired at 125 °C)

Non-heat-resistant trays, such as magazine and taping trays, cannot be baked beforeunpacking.

Pin temperature: 300 °C Max., Duration: 3 sec. Max. (per device side)

Recommendedcondition symbolIR35-107-2

VPSVP15-107-2

Partial heating-

NoteFor the storage period after dry-pack decapsulation, storage conditions are Max. 25 °C, 65 % RH.CautionUse of more than one soldering method should be avoided (except for partial heating).

108

µPD70741NOTES FOR CMOS DEVICES1PRECAUTION AGAINST ESD FOR SEMICONDUCTORSNote:Strong electric field, when exposed to a MOS device, can cause destructionof the gate oxide and ultimately degrade the device operation. Steps mustbe taken to stop generation of static electricity as much as possible, andquickly dissipate it once, when it has occurred. Environmental control mustbe adequate. When it is dry, humidifier should be used. It is recommendedto avoid using insulators that easily build static electricity. Semiconductordevices must be stored and transported in an anti-static container, staticshielding bag or conductive material. All test and measurement toolsincluding work bench and floor should be grounded. The operator shouldbe grounded using wrist strap. Semiconductor devices must not be touchedwith bare hands. Similar precautions need to be taken for PW boards withsemiconductor devices on it.2HANDLING OF UNUSED INPUT PINS FOR CMOSNote:No connection for CMOS device inputs can be cause of malfunction. If noconnection is provided to the input pins, it is possible that an internal inputlevel may be generated due to noise, etc., hence causing malfunction. CMOSdevice behave differently than Bipolar or NMOS devices. Input levels ofCMOS devices must be fixed high or low by using a pull-up or pull-downcircuitry. Each unused pin should be connected to VDD or GND with aresistor, if it is considered to have a possibility of being an output pin. Allhandling related to the unused pins must be judged device by device andrelated specifications governing the devices.3STATUS BEFORE INITIALIZATION OF MOS DEVICESNote:Power-on does not necessarily define initial status of MOS device. Produc-tion process of MOS does not define the initial operation status of the device.Immediately after the power source is turned ON, the devices with resetfunction have not yet been initialized. Hence, power-on does not guaranteeout-pin levels, I/O settings or contents of registers. Device is not initializeduntil the reset signal is received. Reset operation must be executed imme-diately after power-on for devices having reset function.109

µPD70741Regional InformationSome information contained in this document may vary from country to country. Before using any NECproduct in your application, pIease contact the NEC office in your country to obtain a list of authorizedrepresentatives and distributors. They will verify: • Device availability• Ordering information• Product release schedule• Availability of related technical literature• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)• Network requirementsIn addition, trademarks, registered trademarks, export restrictions, and other legal issues may also varyfrom country to country.NEC Electronics Inc. (U.S.)Santa Clara, CaliforniaTel: 408-588-6000 800-366-9782Fax: 408-588-6130 800-729-9288NEC Electronics (Germany) GmbHBenelux OfficeEindhoven, The NetherlandsTel: 040-2445845Fax: 040-2444580NEC Electronics Ltd.Tel: 2886-9318Fax: 2886-9022/9044NEC Electronics Ltd. Seoul BranchSeoul, KoreaTel: 02-528-0303Fax: 02-528-4411NEC Electronics (France) S.A.NEC Electronics (Germany) GmbHDuesseldorf, GermanyTel: 0211-65 03 02Fax: 0211-65 03 490Velizy-Villacoublay, FranceTel: 01-30-67 58 00Fax: 01-30-67 58 99NEC Electronics (UK) Ltd.Milton Keynes, UKTel: 01908-691-133Fax: 01908-670-290NEC Electronics (France) S.A.Spain OfficeMadrid, SpainTel: 01-504-2787Fax: 01-504-2860NEC Electronics Singapore Pte. Ltd.United Square, Singapore 1130Tel: 65-253-8311Fax: 65-250-3583NEC Electronics Taiwan Ltd.Taipei, TaiwanTel: 02-719-2377Fax: 02-719-5951NEC Electronics Italiana s.r.1.Milano, ItalyTel: 02-66 75 41Fax: 02-66 75 42 99NEC Electronics (Germany) GmbHScandinavia OfficeTaeby, SwedenTel: 08-63 80 820Fax: 08-63 80 388NEC do Brasil S.A.Cumbica-Guarulhos-SP, BrasilTel: 011-65-6810Fax: 011-65-6829J98. 2

110

µPD70741[MEMO]

111

µPD70741The related documents indicated in this publication may include preliminary versions. However, preliminary versionsare not marked as such.

V810, V821, and V810 Family are trademarks of NEC Corporation.

No part of this document may be copied or reproduced in any form or by any means without the prior writtenconsent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in thisdocument.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectualproperty rights of third parties by or arising from use of a device described herein or any other liability arisingfrom use of such device. No license, either express, implied or otherwise, is granted under any patents,copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons orproperty arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safetymeasures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:

\"Standard\a customer designated \"quality assurance program\" for a specific application. The recommended applicationsof a device depend on its quality grade, as indicated below. Customers must check the quality grade of eachdevice before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.

The quality grade of NEC devices is \"Standard\" unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade,they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.

M4 96. 5

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