Integrated circuit method with triple patterning

专利名称：Integrated circuit method with triple

patterning

发明人：Chia-Chu Liu,Kuei-Shun Chen,Meng-Wei Chen申请号：US14043371申请日：20131001公开号：US08840796B2公开日：20140923

专利附图：

摘要：The present disclosure provides one embodiment of an integrated circuit (IC)design method. The method includes receiving an IC design layout having a plurality of ICfeatures. The method includes identifying, from the IC design layout, simple features as a

first layout wherein the first layout does not violate design rules; and complex featuresas a second layout wherein the second layout violates the design rules. The methodfurther includes generating a third layout and a fourth layout from the second layoutwherein the third layout includes the complex features and connecting features to meetthe design rules and the fourth layout includes trimming features.

申请人：Taiwan Semiconductor Manufacturing Company, Ltd

地址：Hsin-Chu TW

国籍：TW

代理机构：Haynes and Boone, LLP

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